Keyword: FPGA
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MODAULT01 Thirty Meter Telescope Adaptive Optics Computing Challenges real-time, hardware, controls, operation 36
  • C. Boyer, B.L. Ellerbroek, L. Gilles, L. Wang
    TMT, Pasadena, California, USA
  • S. Browne
    The Optical Sciences Company, Anaheim, California, USA
  • G. Herriot, J.P. Veran
    HIA, Victoria, Canada
  • G.J. Hovey
    DRAO, Penticton, British Columbia, Canada
  The Thirty Meter Telescope (TMT) will be used with Adaptive Optics (AO) systems to allow near diffraction-limited performance in the near-infrared and achieve the main TMT science goals. Adaptive optics systems reduce the effect of the atmospheric distortions by dynamically measuring the distortions with wavefront sensors, performing wavefront reconstruction with a Real Time Controller (RTC), and then compensating for the distortions with wavefront correctors. The requirements for the RTC subsystem of the TMT first light AO system will represent a significant advance over the current generation of astronomical AO control systems. Memory and processing requirements would be at least 2 orders of magnitude greater than the currently most powerful AO systems using conventional approaches, so that innovative wavefront reconstruction algorithms and new hardware approaches will be required. In this paper, we will first present the requirements and challenges for the RTC of the first light AO system, together with the algorithms that have been developed to reduce the memory and processing requirements, and then two possible hardware architectures based on Field Programmable Gate Array (FPGA).  
slides icon Slides MODAULT01 [2.666 MB]  
MOMMU012 A Digital Base-band RF Control System controls, diagnostics, operation, software 82
  • M. Konrad, U. Bonnes, C. Burandt, R. Eichhorn, J. Enders, N. Pietralla
    TU Darmstadt, Darmstadt, Germany
  Funding: Supported by DFG through CRC 634.
The analog RF control system of the S-DALINAC has been replaced by a new digital system. The new hardware consists of an RF module and an FPGA board that have been developed in-house. A self-developed CPU implemented in the FPGA executing the control algorithm allows to change the algorithm without time-consuming synthesis. Another micro-controller connects the FPGA board to a standard PC server via CAN bus. This connection is used to adjust control parameters as well as to send commands from the RF control system to the cavity tuner power supplies. The PC runs Linux and an EPICS IOC. The latter is connected to the CAN bus with a device support that uses the SocketCAN network stack included in recent Linux kernels making the IOC independent of the CAN controller hardware. A diagnostic server streams signals from the FPGAs to clients on the network. Clients used for diagnosis include a software oscilloscope as well as a software spectrum analyzer. The parameters of the controllers can be changed with Control System Studio. We will present the architecture of the RF control system as well as the functionality of its components from a control system developers point of view.
slides icon Slides MOMMU012 [0.087 MB]  
poster icon Poster MOMMU012 [33.544 MB]  
MOPKS007 Design of a Digital Controller for ALPI 80 MHz Resonators cavity, feedback, controls, resonance 174
  • S.V. Barabin
    ITEP, Moscow, Russia
  • G. Bassato
    INFN/LNL, Legnaro (PD), Italy
  We discuss the design of a resonator controller completely based on digital technology. The controller is currently operating at 80 MHz but can be easily adapted to frequencies up to 350MHz; it can work either in "Generator Driven" and in "Self Excited Loop" mode. The signal processing unit is a commercial board (Bittware T2-Pci) with 4 TigerSharc DSPs and a Xilinx Virtex II-Pro FPGA. The front-end board includes five A/D channels supporting a sampling rate in excess of 100M/s and a clock distribution system with a jitter less than 10ps, allowing direct sampling of RF signals with no need of analog downconversion. We present the results of some preliminary tests carried out on a 80 MHz quarter wave resonator installed in the ALPI Linac accelerator at INFN-LNL and discuss possible developments of this project.  
poster icon Poster MOPKS007 [0.931 MB]  
MOPKS010 Fast Orbit Correction for the ESRF Storage Ring feedback, controls, operation, diagnostics 177
  • J.M. Koch, F. Epaud, E. Plouviez, K.B. Scheidt
    ESRF, Grenoble, France
  Up to now, at the ESRF, the correction of the orbit position has been performed with two independent systems: one dealing with the slow movements and one correcting the motion in a range of up to 200Hz but with a limited number of fast BPMs and steerers. These latter will be removed and one unique system will cover the frequency range from DC to 200Hz using all the 224 BPMs and the 96 steerers. Indeed, thanks to the procurement of Libera Brilliance units and the installation of new AC power supplies, it is now possible to access all the Beam positions at a frequency of 10 kHz and to drive a small current in the steerers in a 200Hz bandwidth. The first tests of the correction of the beam position have been performed and will be presented. The data processing will be presented as well with a particular emphasis on the development inside the FPGA.  
MOPKS013 Beam Spill Structure Feedback Test in HIRFL-CSR feedback, extraction, controls, power-supply 186
  • R.S. Mao, P. Li, L.Z. Ma, J.X. Wu, J.W. Xia, J.C. Yang, Y.J. Yuan, T.C. Zhao, Z.Z. Zhou
    IMP, Lanzhou, People's Republic of China
  The slow extraction beam from HIRFL-CSR is used in nuclear physics experiments and heavy ion therapy. 50Hz ripple and harmonics are observed in beam spill. To improve the spill structure, the first set of control system consisting of fast Q-magnet and feedback device based FPGA is developed and installed in 2010, and spill structure feedback test also has been started. The commissioning results with spill feedback system are presented in this paper.  
poster icon Poster MOPKS013 [0.268 MB]  
MOPKS014 Architecture and Control of the Fast Orbit Correction for the ESRF Storage Ring network, storage-ring, controls, device-server 189
  • F. Epaud, J.M. Koch, E. Plouviez
    ESRF, Grenoble, France
  Two years ago, the electronics of all the 224 Beam Position Monitors (BPM) of the ESRF Storage Ring were replaced by the commercial Libera Brilliance units to drastically improve the speed and position resolution of the Orbit measurement. Also, at the start of this year, all the 96 power supplies that drive the Orbit steerers have been replaced by new units that now cover a full DC-AC range up to 200Hz. We are now working on the replacement of the previous Fast Orbit Correction system. This new architecture will also use the 224 Libera Brilliance units and in particular the 10 KHz optical links handled by the Diamond Communication Controller (DCC) which has now been integrated within the Libera FPGA as a standard option. The 224 Liberas are connected together with the optical links to form a redundant network where the data are broadcast and are received by all nodes within 40 μS. The 4 corrections stations will be based on FPGA cards (2 per station) also connected to the FOFB network as additional nodes and using the same DCC firmware on one side and are connected to the steerers power supplies using RS485 electronics standard on the other side. Finally two extra nodes have been added to collect data for diagnostics and to give BPMs positions to the beamlines at high rate. This paper will present the network architecture and the control software to operate this new equipment.  
poster icon Poster MOPKS014 [3.242 MB]  
MOPKS022 BPM System And Orbit Feedback System Deisgn For the Taiwan Photon Source feedback, controls, EPICS, power-supply 207
  • C.H. Kuo, J. Chen, Y.-S. Cheng, P.C. Chiu, K.T. Hsu, K.H. Hu, C.Y. Wu
    NSRRC, Hsinchu, Taiwan
  Taiwan Photon Source (TPS) is a 3 GeV synchrotron light source which is in construction at NSRRC. Latest generation BPM electronics with FPGA enhanced functionality of current generation products was adopted. The prototype is under testing. To achieve its design goal of the TPS and eliminate beam motions due to various perturbation sources, orbit feedback is designed with integration of BPM and corrector control system . The design and implementation of the BPM system will be summarized in this report.  
MOPKS024 A Digital System for Longitudinal Emittance Blow-Up in the LHC controls, feedback, software, synchrotron 215
  • M. Jaussi, M. E. Angoletta, P. Baudrenghien, A.C. Butterworth, J. Sanchez-Quesada, E.N. Shaposhnikova, J. Tückmantel
    CERN, Geneva, Switzerland
  In order to preserve beam stability above injection energy in the LHC, longitudinal emittance blowup is performed during the energy ramp by injecting band-limited noise around the synchrotron frequency into the beam phase loop. The noise is generated continuously in software and streamed digitally into the DSP of the Beam Control system. In order to achieve reproducible results, a feedback system on the observed average bunch length controls the strength of the excitation, allowing the operator to simply set a target bunch length. The frequency spectrum of the excitation depends on the desired bunch length, and as it must follow the evolution of the synchrotron frequency spread through the ramp, it is automatically calculated by the LHC settings management software from the energy and RF voltage. The system is routinely used in LHC operation since August 2010. We present here the details of the implementation in software, FPGA firmware and DSP code, as well as some results with beam.  
poster icon Poster MOPKS024 [0.467 MB]  
MOPKS027 Operational Status of theTransverse Multibunch Feedback System at Diamond feedback, damping, controls, operation 219
  • I. Uzun, M.G. Abbott, M.T. Heron, A.F.D. Morgan, G. Rehm
    Diamond, Oxfordshire, United Kingdom
  A transverse multibunch feedback (TMBF) system is in operation at Diamond Light Source to damp coupled-bunch instabilities up to 250 MHz in both the vertical and horizontal planes. It comprises an in-house designed and built analogue front-end combined with a Libera Bunch-by-Bunch feedback processor and output stripline kickers. FPGA-based feedback electronics is used to implement several diagnostic features in addition to the basic feedback functionality. This paper reports on the current operational status of the TMBF system along with its characteristics. Also discussed are operational diagnostic functionalities including continuous measurement of the betatron tune and chromaticity.  
poster icon Poster MOPKS027 [1.899 MB]  
MOPMN019 Controling and Monitoring the Data Flow of the LHCb Read-out and DAQ Network network, detector, controls, monitoring 281
  • R. Schwemmer, C. Gaspar, N. Neufeld, D. Svantesson
    CERN, Geneva, Switzerland
  The LHCb readout uses a set of 320 FPGA based boards as interface between the on-detector hardware and the GBE DAQ network. The boards are the logical Level 1 (L1) read-out electronics and aggregate the experiment's raw data into event fragments that are sent to the DAQ network. To control the many parameters of the read-out boards, an embedded PC is included on each board, connecting to the boards ICs and FPGAs. The data from the L1 boards is sent through an aggregation network into the High Level Trigger farm. The farm comprises approximately 1500 PCs which at first assemble the fragments from the L1 boards and then do a partial reconstruction and selection of the events. In total there are approximately 3500 network connections. Data is pushed through the network and there is no mechanism for resending packets. Loss of data on a small scale is acceptable but care has to be taken to avoid data loss if possible. To monitor and debug losses, different probes are inserted throughout the entire read-out chain to count fragments, packets and their rates at different positions. To keep uniformity throughout the experiment, all control software was developed using the common SCADA software, PVSS, with the JCOP framework as base. The presentation will focus on the low level controls interface developed for the L1 boards and the networking probes, as well as the integration of the high level user interfaces into PVSS. We will show the way in which the users and developers interact with the software, configure the hardware and follow the flow of data through the DAQ network.  
TUBAUST01 FPGA-based Hardware Instrumentation Development on MAST controls, plasma, hardware, diagnostics 544
  • B.K. Huang, R.M. Myers, R.M. Sharples
    Durham University, Durham, United Kingdom
  • N. Ben Ayed, G. Cunningham, A. Field, S. Khilar, G.A. Naylor
    CCFE, Abingdon, Oxon, United Kingdom
  • R.G.L. Vann
    York University, Heslington, York, United Kingdom
  Funding: This work was part-funded by the RCUK Energy Programme under grant EP/I501045 and the European Communities under the Contract of Association between EURATOM and CCFE.
On MAST (the Mega Amp Spherical Tokamak) at Culham Centre for Fusion Energy some key control systems and diagnostics are being developed and upgraded with FPGA hardware. FPGAs provide many benefits including low latency and real-time digital signal processing. FPGAs blur the line between hardware and software. They are programmed (in VHDL/Verilog language) using software, but once configured act deterministically as hardware. The challenges in developing a system are keeping up-front and maintenance costs low, and prolonging the life of the device as much as possible. We accomplish lower costs by using industry standards such as the FMC (FPGA Mezzanine Card) Vita 57 standard and by using COTS (Commercial Off The Shelf) components which are significantly less costly than developing them in-house. We extend the device operational lifetime by using a flexible FPGA architecture and industry standard interfaces. We discuss the implementation of FPGA control on two specific systems on MAST. The Vertical Stabilisation system comprises of a 1U form factor box with 1 SP601 Spartan6 FPGA board, 10/100 Ethernet access, Microblaze processor, 24-bit σ delta ADS1672 ADC and ATX power supply for remote power cycling. The Electron Bernstein Wave system comprises of a 4U form factor box with 2 ML605 Virtex6 FPGA boards, Gigabit Ethernet, Microblaze processor and 2 FMC108 ADC providing 16 Channels with 14-bit at 250MHz. AXI4 is used as the on chip bus between firmware components to allow very high data rates which has been tested at over 40Gbps streaming into a 2GB DDR3 SODIMM.
slides icon Slides TUBAUST01 [8.172 MB]  
TUBAUST02 FPGA Communications Based on Gigabit Ethernet Ethernet, interface, hardware, controls 547
  • L.R. Doolittle, C. Serrano
    LBNL, Berkeley, California, USA
  The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and affordability. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip- and board-independent FPGA design which implements the Gigabit Ethernet standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer.  
slides icon Slides TUBAUST02 [0.909 MB]  
TUBAULT03 The Upgrade Path from Legacy VME to VXS Dual Star Connectivity for Large Scale Data Acquisition and Trigger Systems hardware, detector, fibre-optics, data-acquisition 550
  • C. Cuevas, D. Abbott, F.J. Barbosa, H. Dong, W. Gu, E. Jastrzembski, S.R. Kaneta, B. Moffit, N. Nganga, B.J. Raydo, A. Somov, W.M. Taylor, J. Wilson
    JLAB, Newport News, Virginia, USA
  Funding: Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177
New instrumentation modules have been designed by Jefferson Lab and to take advantage of the higher performance and elegant backplane connectivity of the VITA 41 VXS standard. These new modules are required to meet the 200KHz trigger rates envisioned for the 12GeV experimental program. Upgrading legacy VME designs to the high speed gigabit serial extensions that VXS offers, comes with significant challenges, including electronic engineering design, plus firmware and software development issues. This paper will detail our system design approach including the critical system requirement stages, and explain the pipeline design techniques and selection criteria for the FPGA that require embedded Gigabit serial transceivers. The entire trigger system is synchronous and operates at 250MHz clock with synchronization signals, and the global trigger signals distributed to each front end readout crate via the second switch slot in the 21 slot, dual star VXS backplane. The readout of the buffered detector signals relies on 2eSST over the standard VME64x path at >200MB/s. We have achieved 20Gb/s transfer rate of trigger information within one VXS crate and will present results using production modules in a two crate test configuration with both VXS crates fully populated. The VXS trigger modules that reside in the front end crates, will be ready for production orders by the end of the 2011 fiscal year. VXS Global trigger modules are in the design stage now, and will be complete to meet the installation schedule for the 12GeV Physics program.
slides icon Slides TUBAULT03 [7.189 MB]  
TUBAULT04 Open Hardware for CERN’s Accelerator Control Systems hardware, controls, software, timing 554
  • E. Van der Bij, P. Alvarez, M. Ayass, A. Boccardi, M. Cattin, C. Gil Soriano, E. Gousiou, S. Iglesias Gonsálvez, G. Penacoba Fernandez, J. Serrano, N. Voumard, T. Włostowski
    CERN, Geneva, Switzerland
  The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its collaborators. To attract other partners, that are not necessarily part of the existing networks of particle physics, the new projects are developed in a fully 'Open' fashion. This allows for strong collaborations that will result in better and reusable designs. Within this Open Hardware project new ways of working with industry are being tested with the aim to prove that there is no contradiction between commercial off-the-shelf products and openness and that industry can be involved at all stages, from design to production and support.  
slides icon Slides TUBAULT04 [7.225 MB]  
WEBHMULT04 Sub-nanosecond Timing System Design and Development for LHAASO Project detector, Ethernet, timing, network 646
  • G.H. Gong, S. Chen, Q. Du, J.M. Li, Y. Liu
    Tsinghua University, Beijing, People's Republic of China
  • H. He
    IHEP Beijing, Beijing, People's Republic of China
  Funding: National Science Foundation of China (No.11005065)
The Large High Altitude Air Shower Observatory (LHAASO) [1] project is designed to trace galactic cosmic ray sources by approximately 10,000 different types of ground air shower detectors. Reconstruction of cosmic ray arrival directions requires sub-nanosecond time synchronization, a novel design of the LHAASO timing system by means of packet-based frequency distribution and time synchronization over Ethernet is proposed. The White Rabbit Protocol (WR) [2] is applied as the infrastructure of the timing system, which implements a distributed adaptive phase tracking technology based on Synchronous Ethernet to lock all local clocks, and a real time delay calibration method based on the Precision Time Protocol to keep all local time synchronized within a nanosecond. We also demonstrate the development and test status on prototype WR switches and nodes.
[1] Cao Zhen, "A future project at tibet: the large high altitude air shower observatory (LHAASO)", Chinese Phys. C 34 249,2010
[2] P. Moreira, et al, "White Rabbit: Sub-Nanosecond Timing Distribution over Ethernet", ISPCS 2009
slides icon Slides WEBHMULT04 [8.775 MB]  
WEMMU001 Floating-point-based Hardware Accelerator of a Beam Phase-Magnitude Detector and Filter for a Beam Phase Control System in a Heavy-Ion Synchrotron Application detector, controls, hardware, synchrotron 683
  • F.A. Samman
    Technische Universität Darmstadt, Darmstadt, Germany
  • M. Glesner, C. Spies, S. Surapong
    TUD, Darmstadt, Germany
  Funding: German Federal Ministry of Education and Research in the frame of Project FAIR (Facility for Antiproton and Ion Research), Grant Number 06DA9028I.
A hardware implementation of an adaptive phase and magnitude detector and filter of a beam-phase control system in a heavy ion synchrotron application is presented in this paper [1]. The main components of the hardware are adaptive LMS filters and a phase and magnitude detector. The phase detectors are implemented by using a CORDIC algorithm based on 32-bit binary floating-point arithmetic data formats. Therefore, a decimal to floating-point adapter is required to interface the data from an ADC to the phase and magnitude detector. The floating-point-based hardware is designed to improve the precision of the past hardware implementation that is based on fixed-point arithmetics. The hardware of the detector and the adaptive LMS filter have been implemented on a reconfigurable FPGA device for hardware acceleration purpose. The ideal Matlab/Simulink model of the hardware and the VHDL model of the adaptive LMS filter and the phase and magnitude detector are compared. The comparison result shows that the output signal of the floating-point based adaptive FIR filter as well as the phase and magnitude detector is simillar to the expected output signal of the ideal Matlab/Simulink model.
[1] H. Klingbeil, "A Fast DSP-Based Phase-Detector for Closed-Loop RF Control in Synchrotrons," IEEE Trans. Instrum. Meas., 54(3):1209–1213, 2005.
slides icon Slides WEMMU001 [0.383 MB]  
WEMMU004 SPI Boards Package, a New Set of Electronic Boards at Synchrotron SOLEIL controls, undulator, detector, interface 687
  • Y.-M. Abiven, P. Betinelli-Deck, J. Bisou, F. Blache, F. Briquez, A. Chattou, J. Coquet, P. Gourhant, N. Leclercq, P. Monteiro, G. Renaud, J.P. Ricaud, L. Roussier
    SOLEIL, Gif-sur-Yvette, France
  SOLEIL is a third generation Synchrotron radiation source located in France near Paris. At the moment, the Storage Ring delivers photon beam to 23 beamlines. Since machine and beamlines improve their performance, new requirements are identified. On the machine side, new implementation for feedforward of electromagnetic undulators is required to improve beam stability. On the beamlines side, a solution is required to synchronize data acquisition with motor position during continuous scan. In order to provide a simple and modular solution for these applications requiring synchronization, the electronic group developed a set of electronic boards called "SPI board package". In this package, the boards can be connected together in daisy chain and communicate to the controller through a SPI* Bus. Communication with control system is done via Ethernet. At the moment the following boards are developed: a controller board based on a Cortex M3 MCU, 16bits ADC board, 16bits DAC board and a board allowing to process motor encoder signals based on a FPGA Spartan III. This platform allows us to embed process close to the hardware with open tools. Thanks to this solution we reach the best performances of synchronization.
* SPI: Serial Peripheral Interface
slides icon Slides WEMMU004 [0.230 MB]  
poster icon Poster WEMMU004 [0.430 MB]  
WEMMU010 Dependable Design Flow for Protection Systems using Programmable Logic Devices hardware, simulation, controls, software 706
  • M. Kwiatkowski, B. Todd
    CERN, Geneva, Switzerland
  Programmable Logic Devices (PLD) such as Field Programmable Gate Arrays (FPGA) are becoming more prevalent in protection and safety-related electronic systems. When employing such programmable logic devices, extra care and attention needs to be taken. It is important to be confident that the final synthesis result, used to generate the bit-stream to program the device, meets the design requirements. This paper will describe how to maximize confidence using techniques such as Formal Methods, exhaustive Hardware Description Language (HDL) code simulation and hardware testing. An example will be given for one of the critical function of the Safe Machine Parameters (SMP) system, one of the key systems for the protection of the Large Hadrons Collider (LHC) at CERN. The design flow will be presented where the implementation phase is just one small element of the whole process. Techniques and tools presented can be applied for any PLD based system implementation and verification.  
slides icon Slides WEMMU010 [1.093 MB]  
poster icon Poster WEMMU010 [0.829 MB]  
WEPKN015 A New Helmholtz Coil Permanent Magnet Measurement System* controls, data-acquisition, interface, permanent-magnet 738
  • J.Z. Xu, I. Vasserman
    ANL, Argonne, USA
  Funding: Work supported by U.S. Department of Energy Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.
A new Helmholtz Coil magnet measurement system has been developed at the Advanced Phone Source (APS) to characterize and sort the insertion device permanent magnets. The system uses the latest state-of-the-art field programmable gate array (FPGA) technology to compensate the speed variations of the magnet motion. Initial results demonstrate that the system achieves a measurement precision better than 0.001 ampere-meters squared (A·m2) in a permanent magnet moment measurement of 32 A·m2, probably the world's best precision of its kind.
poster icon Poster WEPKN015 [0.710 MB]  
WEPMN006 Commercial FPGA Based Multipurpose Controller: Implementation Perspective EPICS, hardware, GUI, controls 882
  • I. Arredondo, D. Belver, P. Echevarria, M. Eguiraun, H. Hassanzadegan, M. del Campo
    ESS-Bilbao, Zamudio, Spain
  • V. Etxebarria, J. Jugo
    University of the Basque Country, Faculty of Science and Technology, Bilbao, Spain
  • N. Garmendia, L. Muguira
    ESS Bilbao, Bilbao, Spain
  Funding: The present work is supported by the Basque Government and Spanish Ministry of Science and Innovation.
This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,…), methods to create and use the EPICS server (put, get, monitor,…), mathematical methods to process the data (numeric format conversions,…) and methods to create/initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. It is the developed main class which is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao facility.
poster icon Poster WEPMN006 [0.559 MB]  
WEPMN016 Synchronously Driven Power Converter Controller Solution for MedAustron timing, interface, controls, real-time 912
  • L. Šepetavc, J. Dedič, R. Tavčar
    Cosylab, Ljubljana, Slovenia
  • J. Gutleber
    CERN, Geneva, Switzerland
  • R. Moser
    EBG MedAustron, Wr. Neustadt, Austria
  MedAustron is an ion beam cancer therapy and research centre currently under construction in Wiener Neustadt, Austria. This facility features a synchrotron particle accelerator for light ions. Cosylab is closely working together with MedAustron on the development of a power converter controller (PCC) for the 260 deployed converters. The majority are voltage sources that are regulated in real-time via digital signal processor (DSP) boards. The in-house developed PCC operates the DSP boards remotely, via real-time fiber optic links. A single PCC will control up to 30 power converters that deliver power to magnets used for focusing and steering particle beams. Outputs of all PCCs must be synchronized within a time frame of at most 1 microsecond, which is achieved by integration with the timing system. This pulse-to-pulse modulation machine requires different waveforms for each beam generation cycle. Dead times between cycles must be kept low, therefore the PCC is reconfigured during beam generation. The system is based on a PXI platform from National Instruments running LabVIEW Real-Time. An in-house developed generic real-time optical link connects the PCCs to custom developed front-end devices. These FPGA-based hardware components facilitate integration with different types of power converters. All PCCs are integrated within the SIMATIC WinCC OA SCADA system which coordinates and supervises their operation. This paper describes the overall system architecture, its main components, challenges we faced and the technical solutions.  
poster icon Poster WEPMN016 [0.695 MB]  
WEPMN018 Performance Tests of the Standard FAIR Equipment Controller Prototype controls, timing, Ethernet, software 919
  • S. Rauch, R. Bär, W. Panschow, M. Thieme
    GSI, Darmstadt, Germany
  For the control system of the new FAIR accelerator facility a standard equipment controller, the Scalable Control Unit (SCU), is presently under development. First prototypes have already been tested in real applications. The controller combines an x86 ComExpress Board and an Altera Arria II FPGA. Over a parallel bus interface called the SCU bus, up to 12 slave boards can be controlled. Communication between CPU and FPGA is done by a PCIe link. We discuss the real time behaviour between the Linux OS and the FPGA Hardware. For the test, a Front-End Software Architecture (FESA) class, running under Linux, communicates with the PCIe bridge in the FPGA. Although we are using PCIe only for single 32 bit wide accesses to the FPGA address space, the performance still seems sufficient. The tests showed an average response time to IRQs of 50 microseconds with a 1.6 GHz Intel Atom CPU. This includes the context change to the FESA userspace application and the reply back to the FPGA. Further topics are the bandwidth of the PCIe link for single/burst transfers and the performance of the SCU bus communication.  
WEPMN024 NSLS-II Beam Position Monitor Embedded Processor and Control System embedded, controls, EPICS, Ethernet 932
  • K. Ha, L.R. Dalesio, J.H. De Long, J. Mead, Y. Tian, K. Vetter
    BNL, Upton, New York, USA
  Funding: Work supported by DOE contract No: DE-AC02-98CH10886
NSLS-II is a 3 Gev 3rd generation light source that is currently under construction. A sub-micron Digital Beam Position Monitor (DBPM) system which is hardware electronics and embedded software processor and EPICS IOC has been successfully developed and tested in the ALS storage ring and BNL Lab.
WEPMN025 A New Fast Triggerless Acquisition System For Large Detector Arrays detector, real-time, controls, experiment 935
  • P. Mutti, M. Jentschel, J. Ratel, F. Rey, E. Ruiz-Martinez, W. Urban
    ILL, Grenoble, France
  Presently a common characteristic trend in low and medium energy nuclear physics is to develop more complex detector systems to form multi-detector arrays. The main objective of such an elaborated set-up is to obtain comprehensive information about the products of all reactions. State-of-art γ-ray spectroscopy requires nowadays the use of large arrays of HPGe detectors often coupled with anti-Compton active shielding to reduce the ambient background. In view of this complexity, the front-end electronics must provide precise information about energy, time and possibly pulse shape. The large multiplicity of the detection system requires the capability to process the multitude of signals from many detectors, fast processing and very high throughput of more that 106 data words/sec. The possibility to handle such a complex system using traditional analogue electronics has shown rapidly its limitation due, first of all, to the non negligible cost per channel and, moreover, to the signal degradation associated to complex analogue path. Nowadays, digital pulse processing systems are available, with performances, in terms of timing and energy resolution, equal when not better than the corresponding analogue ones for a fraction of the cost per channel. The presented system uses a combination of a 15-bit 100 MS/s digitizer with a PowerPC-based VME single board computer. Real-time processing algorithms have been developed to handle total event rates of more than 1 MHz, providing on-line display for single and coincidence events.  
poster icon Poster WEPMN025 [15.172 MB]  
WEPMN028 Development of Image Data Acquisition System for 2D Detector at SACLA (SPring-8 XFEL) detector, data-acquisition, interface, laser 947
  • A. Kiyomichi, A. Amselem, T. Hirono, T. Ohata, R. Tanaka, M. Yamaga
    JASRI/SPring-8, Hyogo-ken, Japan
  • T. Hatsui
    RIKEN/SPring-8, Hyogo, Japan
  The x-ray free electron laser facility SACLA (SPring-8 Angstrom Compact free electron LAser) was constructed and started beam commissioning from March 2011. For the requirements of proposed experiments at SACLA, x-ray multi-readout ports CCD detectors (MPCCD) have been developed to realize a system with the total amount of 4 Mega-pixels area and 16bit wide dynamic range at a frame rate of 60Hz shot rate. We have developed the image data-handling scheme using the event-synchronized data-acquisition system. The front-end system used the CameraLink interface that excels in abilities of real-time triggering and high-speed data transfer. For the total data rate up to 4Gbps, the image data are collected by dividing the CCD detector into eight segments, which handles 0.5M pixels each, and then sent to high-speed data storage in parallel. We prepared two types of Cameralink imaging system for the VME and PC base. The Image Distribution board is made up of logic-reconfigurable VME board with CameraLink mezzanine card. The front-end system of MPCCD detector consists of eight sets of Image Distribution boards. We plan to introduce the online lossless compression using FPGA with arithmetic coding algorithm. For wide adaptability of user requirements, we also prepared the PC based imaging system, which consists of Linux server and commercial CameraLink PCI interface. It does not contain compression function, but supports various type of CCD camera, for example, high-definition (1920x1080) single CCD camera.  
poster icon Poster WEPMN028 [5.574 MB]  
WEPMS011 The Timing Master for the FAIR Accelerator Facility timing, network, embedded, real-time 996
  • R. Bär, T. Fleck, M. Kreider, S. Mauro
    GSI, Darmstadt, Germany
  One central design feature of the FAIR accelerator complex is a high level of parallel beam operation, imposing ambitious demands on the timing and management of accelerator cycles. Several linear accelerators, synchrotrons, storage rings and beam lines have to be controlled and re-configured for each beam production chain on a pulse-to-pulse basis, with cycle lengths ranging from 20 ms to several hours. This implies initialization, synchronization of equipment on the time scale down to the ns level, interdependencies, multiple paths and contingency actions like emergency beam dump scenarios. The FAIR timing system will be based on White Rabbit [1] network technology, implementing a central Timing Master (TM) unit to orchestrate all machines. The TM is subdivided into separate functional blocks: the Clock Master, which deals with time and clock sources and their distribution over WR, the Management Master, which administrates all WR timing receivers, and the Data Master, which schedules and coordinates machine instructions and broadcasts them over the WR network. The TM triggers equipment actions based on the transmitted execution time. Since latencies in the low μs range are required, this paper investigates the possibilities of parallelisation in programmable hardware and discusses the benefits to either a distributed or monolithic timing master architecture. The proposed FPGA based TM will meet said timing requirements while providing fast reaction to interlocks and internal events and offers parallel processing of multiple signals and state machines.
[1] J. Serrano, et al, "The White Rabbit Project", ICALEPCS 2009.
WEPMS016 Network on Chip Master Control Board for Neutron's Acquisition neutron, interface, controls, network 1006
  • E. Ruiz-Martinez, T. Mary, P. Mutti, J. Ratel, F. Rey
    ILL, Grenoble, France
  In the neutron scattering instruments at the Institute Laue-Langevin, one of the main challenges for the acquisition control is to generate the suitable signalling for the different modes of neutron acquisition. An inappropriate management could cause loss of information during the course of the experiments and in the subsequent data analysis. It is necessary to define a central element to provide synchronization to the rest of the units. The backbone of the proposed acquisition control system is the denominated master acquisition board. This main board is designed to gather together the modes of neutron acquisition used in the facility, and make it common for all the instruments in a simple, modular and open way, giving the possibility of adding new performances. The complete system also includes a display board and n histogramming modules connected to the neutrons detectors. The master board consists of a VME64X configurable high density I/O connection carrier board based on latest Xilinx Virtex-6T FPGA. The internal architecture of the FPGA is designed as a Network on Chip (NoC) approach. It represents a switch able to communicate efficiently the several resources available in the board (PCI Express, VME64x Master/Slave, DDR3 controllers and user's area). The core of the global signal synchronization is fully implemented in the FPGA, the board has a completely user configurable IO front-end to collect external signals, to process them and to distribute the synchronization control via the bus VME to the others modules involved in the acquisition.  
poster icon Poster WEPMS016 [7.974 MB]  
WEPMS017 The Global Trigger Processor: A VXS Switch Module for Triggering Large Scale Data Acquisition Systems Ethernet, interface, hardware, embedded 1010
  • S.R. Kaneta, C. Cuevas, H. Dong, W. Gu, E. Jastrzembski, N. Nganga, B.J. Raydo, J. Wilson
    JLAB, Newport News, Virginia, USA
  Funding: Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177.
The 12 GeV upgrade for Jefferson Lab's Continuous Electron Beam Accelerator Facility requires the development of a new data acquisition system to accommodate the proposed 200 kHz Level 1 trigger rates expected for fixed target experiments at 12 GeV. As part of a suite of trigger electronics comprised of VXS switch and payload modules, the Global Trigger Processor (GTP) will handle up to 32,768 channels of preprocessed trigger information data from the multiple detector systems that surround the beam target at a system clock rate of 250 MHz. The GTP is configured with user programmable Physics trigger equations and when trigger conditions are satisfied, the GTP will activate the storage of data for subsequent analysis. The GTP features an Altera Stratix IV GX FPGA allowing interface to 16 Sub-System Processor modules via 32 5-Gbps links, DDR2 and flash memory devices, two gigabit Ethernet interfaces using Nios II embedded processors, fiber optic transceivers, and trigger output signals. The GTP's high-bandwidth interconnect with the payload modules in the VXS crate, the Ethernet interface for parameter control, status monitoring, and remote update, and the inherent nature of its FPGA give it the flexibility to be used large variety of tasks and adapt to future needs. This paper details the responsibilities of the GTP, the hardware's role in meeting those requirements, and elements of the VXS architecture that facilitated the design of the trigger system. Also presented will be the current status of development including significant milestones and challenges.
poster icon Poster WEPMS017 [0.851 MB]  
WEPMS019 Measuring Angle with Pico Meter Resolution electronics, laser, ion, controls 1014
  • P. Mutti, M. Jentschel, T. Mary, F. Rey
    ILL, Grenoble, France
  • G. Mana, E. Massa
    INRIM, Turin, Italy
  The kilogram is the only remaining fundamental unit within the SI system that is defined in terms of a material artefact (a PtIr cylinder kept in Paris). Therefore, one of the major tasks of modern metrology is the redefinition of the kilogram on the basis of a natural quantity or of a fundamental constant. However, any kilogram redefinition must approach a 10-8 relative accuracy in its practical realization. A joint research project amongst the major metrology institutes in Europe has proposed the redefinition of the kilogram based on the mass of the 12C atom. The goal can be achieved by counting in a first step the number of atoms in a macroscopic weighable object and, in a second step, by weighing the atom by means of measuring its Compton frequency vC. It is in the second step of the procedure, where the ILL is playing a fundamental role with GAMS, the high-resolution γ-ray spectrometer. Energies of the γ-rays emitted in the decay of the capture state to the ground state of a daughter nucleus after a neutron capture reaction can be measured with high precision. In order to match the high demand in angle measurement accuracy, a new optical interferometer with 10 picorad resolution and linearity over a total measurement range of 15° and high stability of about 0.1 nrad/hour has been developed. To drive the interferometer, a new FPGA based electronics for the heterodyne frequency generation and for real time phase measurement and axis control has been realized. The basic concepts of the FPGA implementation will be revised.  
poster icon Poster WEPMS019 [6.051 MB]  
WEPMS026 The TimBel Synchronization Board for Time Resolved Experiments at Synchrotron SOLEIL synchrotron, experiment, electron, storage-ring 1036
  • J.P. Ricaud, P. Betinelli-Deck, J. Bisou, X. Elattaoui, C. Laulhé, P. Monteiro, L.S. Nadolski, S. Ravy, G. Renaud, M.G. Silly, F. Sirotti
    SOLEIL, Gif-sur-Yvette, France
  Time resolved experiments are one of the major services that synchrotrons can provide to scientists. The short, high frequency and regular flashes of synchrotron light are a fantastic tool to study the evolution of phenomena over time. To carry out time resolved experiments, beamlines need to synchronize their devices with these flashes of light with a jitter shorter than the pulse duration. For that purpose, Synchrotron SOLEIL has developed the TimBeL board fully interfaced to TANGO framework. This paper presents the main features required by time resolved experiments and how we achieved our goals with the TimBeL board.  
poster icon Poster WEPMS026 [1.726 MB]  
WEPMU002 Testing Digital Electronic Protection Systems hardware, LabView, software, controls 1047
  • A. Garcia Muñoz, S. Gabourin
    CERN, Geneva, Switzerland
  The Safe Machine Parameters Controller (SMPC) ensures the correct configuration of the LHC machine protection system, and that safe injection conditions are maintained throughout the filling of the LHC machine. The SMPC receives information in real-time from measurement electronics installed throughout the LHC and SPS accelerators, determines the state of the machine, and informs the SPS and LHC machine protection systems of these conditions. This paper outlines the core concepts and realization of the SMPC test-bench, based on a VME crate and LabVIEW program. Its main goal is to ensure the correct function of the SMPC for the protection of the CERN accelerator complex. To achieve this, the tester has been built to replicate the machine environment and operation, in order to ensure that the chassis under test is completely exercised. The complexity of the task increases with the number of input combinations which are, in the case of the SMPC, in excess of 2364. This paper also outlines the benefits and weaknesses of developing a test suite independently of the hardware being tested, using the "V" approach.  
poster icon Poster WEPMU002 [0.763 MB]  
WEPMU013 Development of a Machine Protection System for the Superconducting Beam Test Facility at FERMILAB controls, laser, operation, status 1084
  • L.R. Carmichael, M.D. Church, R. Neswold, A. Warner
    Fermilab, Batavia, USA
  Funding: Operated by Fermi Research Alliance, LLC under Contract No. DE-AC02-07CH11359 with the United States Department of Energy.
Fermilab’s Superconducting RF Beam Test Facility currently under construction will produce electron beams capable of damaging the acceleration structures and the beam line vacuum chambers in the event of an aberrant accelerator pulse. The accelerator is being designed with the capability to operate with up to 3000 bunches per macro-pulse, 5Hz repetition rate and 1.5 GeV beam energy. It will be able to sustain an average beam power of 72 KW at the bunch charge of 3.2 nC. Operation at full intensity will deposit enough energy in niobium material to approach the melting point of 2500 °C. In the early phase with only 3 cryomodules installed the facility will be capable of generating electron beam energies of 810 MeV and an average beam power that approaches 40 KW. In either case a robust Machine Protection System (MPS) is required to mitigate effects due to such large damage potentials. This paper will describe the MPS system being developed, the system requirements and the controls issues under consideration.
poster icon Poster WEPMU013 [0.755 MB]  
WEPMU015 The Machine Protection System for the R&D Energy Recovery LINAC LabView, hardware, software, interface 1087
  • Z. Altinbas, J.P. Jamilkowski, D. Kayran, R.C. Lee, B. Oerter
    BNL, Upton, Long Island, New York, USA
  Funding: Work supported by Brookhaven Science Associates, LLC under Contract No. DE-AC02-98CH10886 with the U.S. Department of Energy.
The Machine Protection System (MPS) is a device-safety system that is designed to prevent damage to hardware by generating interlocks, based upon the state of input signals generated by selected sub-systems. It protects all the key machinery in the R&D Project called the Energy Recovery LINAC (ERL) against the high beam current. The MPS is capable of responding to a fault with an interlock signal within several microseconds. The ERL MPS is based on a National Instruments CompactRIO platform, and is programmed by utilizing National Instruments' development environment for a visual programming language. The system also transfers data (interlock status, time of fault, etc.) to the main server. Transferred data is integrated into the pre-existing software architecture which is accessible by the operators. This paper will provide an overview of the hardware used, its configuration and operation, as well as the software written both on the device and the server side.
poster icon Poster WEPMU015 [17.019 MB]  
WEPMU018 Real-time Protection of the "ITER-like Wall at JET" real-time, controls, plasma, network 1096
  • M.B. Jouve, C. Balorin
    Association EURATOM-CEA, St Paul Lez Durance, France
  • G. Arnoux, S. Devaux, D. Kinna, P.D. Thomas, K-D. Zastrow
    CCFE, Abingdon, Oxon, United Kingdom
  • P.J. Carvalho
    IPFN, Lisbon, Portugal
  • J. Veyret
    Sundance France, Matignon, France
  During the last JET tokamak shutdown a new ITER-Like Wall was installed using Tungsten and Beryllium materials. To ensure plasma facing component (PFC) integrity, the real-time protection of the wall has been upgraded through the project "Protection for the ITER-like Wall" (PIW). The choice has been made to work with 13 CCD robust analog cameras viewing the main areas of plasma wall interaction and to use regions of interest (ROI) for monitoring in real time the surface temperature of the PFCs. For each camera, ROIs will be set up pre-pulse and, during plasma operation, surface temperatures from these ROIs will be sent to the real time processing system for monitoring and eventually preventing damages on PFCs by modifying the plasma parameters. The video and the associated control system developed for this project is presented in this paper. The video is captured using PLEORA frame grabber and it is sent on GigE network to the real time processing system (RTPS) divided into a 'Real time processing unit' (RTPU), for surface temperature calculation, and the 'RTPU Host', for connection between RTPU and other systems. The RTPU design is based on commercial Xilinx Virtex5 FPGA boards with one board per camera and 2 boards per host. Programmed under Simulink using System generator blockset, the field programmable gate array (FPGA) can manage simultaneously up to 96 ROI defined pixel by pixel.  
poster icon Poster WEPMU018 [2.450 MB]  
WEPMU020 LHC Collimator Controls for a Safe LHC Operation controls, injection, survey, operation 1104
  • S. Redaelli, R.W. Assmann, M. Donzé, R. Losito, A. Masi
    CERN, Geneva, Switzerland
  The beam stored energy at the Large Hadron Collider (LHC) will be up to 360 MJ, to be compared with the quench limit of super-conducting magnets of a few mJ per cm3 and with the damage limit of metal of a few hundreds kJ. The LHC collimation system is designed to protect the machine against beam losses and consists of 108 collimators, 100 of which are movable, located along the 27 km long ring and in the transfer lines. Each collimator has two jaws controlled by four stepping motors to precisely adjust collimator position and angle with respect to the beam. Stepping motors have been used to ensure high position reproducibility. LVDT and resolvers have been installed to monitor in real-time at 100 Hz the jaw positions and the collimator gaps. The cleaning performance and machine protection role of the system depend critically on the accurate jaw positioning. A fully redundant survey system has been developed to ensure that the collimators dynamically follow optimum settings in all phases of the LHC operational cycle. Jaw positions and collimator gaps are interlocked against dump limits defined redundantly as functions of the time, of the beam energy and of the beta* functions that describes the focusing property of the beams. In this paper, the architectural choices that guarantee a safe LHC operation are presented. Hardware and software implementations that ensure the required reliability are described. The operational experience accumulated so far is reviewed and a detailed failure analysis that show the fulfillment of the machine protection specifications is presented.  
THAAUST01 Tailoring the Hardware to Your Control System controls, EPICS, hardware, interface 1171
  • E. Björklund, S.A. Baily
    LANL, Los Alamos, New Mexico, USA
  Funding: Work supported by the US Department of Energy under contract DE-AC52-06NA25396
In the very early days of computerized accelerator control systems the entire control system, from the operator interface to the front-end data acquisition hardware, was custom designed and built for that one machine. This was expensive, but the resulting product was a control system seamlessly integrated (mostly) with the machine it was to control. Later, the advent of standardized bus systems such as CAMAC, VME, and CANBUS, made it practical and attractive to purchase commercially available data acquisition and control hardware. This greatly simplified the design but required that the control system be tailored to accommodate the features and eccentricities of the available hardware. Today we have standardized control systems (Tango, EPICS, DOOCS) using commercial hardware on standardized busses. With the advent of FPGA technology and programmable automation controllers (PACs & PLCs) it now becomes possible to tailor commercial hardware to the needs of a standardized control system and the target machine. In this paper, we will discuss our experiences with tailoring a commercial industrial I/O system to meet the needs of the EPICS control system and the LANSCE accelerator. We took the National Instruments Compact RIO platform, embedded an EPICS IOC in its processor, and used its FPGA backplane to create a "standardized" industrial I/O system (analog in/out, binary in/out, counters, and stepper motors) that meets the specific needs of the LANSCE accelerator.
slides icon Slides THAAUST01 [0.812 MB]  
THCHMUST03 A New Fast Data Logger and Viewer at Diamond: the FA Archiver network, feedback, electron, target 1244
  • M.G. Abbott, G. Rehm, I. Uzun
    Diamond, Oxfordshire, United Kingdom
  At the Diamond Light Source position data from 168 Electron Beam Position Monitors (BPMs) and some X-Ray BPMs is distributed over the Fast Acquisition communications network at an update rate of 10kHz; the total aggregate data rate is around 15MB/s. The data logger described here (the FA Archiver) captures this entire data stream to disk in real time, re-broadcasts selected subsets of the live stream to interested clients, and allows rapid access to any part of the saved data. The archive is saved into a rolling buffer allowing retrieval of detailed beam position data from any time in the last four days. A simple socket-based interface to the FA Archiver allows easy access to both the stored and live data from a variety of clients. Clients include a graphical viewer for visualising the motion or spectrum of a single BPM in real time, a command line tool for retrieving any part of the stored data by time of day, and Matlab scripts for exploring the dataset, helped by the storage of decimated minimum, maximum, and mean data.  
slides icon Slides THCHMUST03 [0.482 MB]  
THCHMUST04 Free and Open Source Software at CERN: Integration of Drivers in the Linux Kernel Linux, controls, framework, data-acquisition 1248
  • J.D. González Cobas, S. Iglesias Gonsálvez, J.H. Lewis, J. Serrano, M. Vanga
    CERN, Geneva, Switzerland
  • E.G. Cota
    Columbia University, NY, USA
  • A. Rubini, F. Vaga
    University of Pavia, Pavia, Italy
  We describe the experience acquired during the integration of the tsi148 driver into the main Linux kernel tree. The benefits (and some of the drawbacks) for long-term software maintenance are analysed, the most immediate one being the support and quality review added by an enormous community of skilled developers. Indirect consequences are also analysed, and these are no less important: a serious impact in the style of the development process, the use of cutting edge tools and technologies supporting development, the adoption of the very strict standards enforced by the Linux kernel community, etc. These elements were also exported to the hardware development process in our section and we will explain how they were used with a particular example in mind: the development of the FMC family of boards following the Open Hardware philosophy, and how its architecture must fit the Linux model. This delicate interplay of hardware and software architectures is a perfect showcase of the benefits we get from the strategic decision of having our drivers integrated in the kernel. Finally, the case for a whole family of CERN-developed drivers for data acquisition models, the prospects for its integration in the kernel, and the adoption of a model parallel to Comedi, is also taken as an example of how this model will perform in the future.  
slides icon Slides THCHMUST04 [0.777 MB]  
THCHMUST05 The Case for Soft-CPUs in Accelerator Control Systems software, hardware, controls, Linux 1252
  • W.W. Terpstra
    GSI, Darmstadt, Germany
  The steady improvements in Field Programmable Gate Array (FPGA) performance, size, and cost have driven their ever increasing use in science and industry. As FPGA sizes continue to increase, more and more devices and logic are moved from external chips to FPGAs. For simple hardware devices, the savings in board area and ASIC manufacturing setup are compelling. For more dynamic logic, the trade-off is not always as clear. Traditionally, this has been the domain of CPUs and software programming languages. In hardware designs already including an FPGA, it is tempting to remove the CPU and implement all logic in the FPGA, saving component costs and increasing performance. However, that logic must then be implemented in the more constraining hardware description languages, cannot be as easily debugged or traced, and typically requires significant FPGA area. For performance-critical tasks this trade-off can make sense. However, for the myriad slower and dynamic tasks, software programming languages remain the better choice. One great benefit of a CPU is that it can perform many tasks. Thus, by including a small "Soft-CPU" inside the FPGA, all of the slower tasks can be aggregated into a single component. These tasks may then re-use existing software libraries, debugging techniques, and device drivers, while retaining ready access to the FPGA's internals. This paper discusses requirements for using Soft-CPUs in this niche, especially for the FAIR project. Several open-source alternatives will be compared and recommendations made for the best way to leverage a hybrid design.  
slides icon Slides THCHMUST05 [0.446 MB]  
THCHMUST06 The FAIR Timing Master: A Discussion of Performance Requirements and Architectures for a High-precision Timing System timing, controls, kicker, network 1256
  • M. Kreider
    GSI, Darmstadt, Germany
  • M. Kreider
    Hochschule Darmstadt, University of Applied Science, Darmstadt, Germany
  Production chains in a particle accelerator are complex structures with many interdependencies and multiple paths to consider. This ranges from system initialisation and synchronisation of numerous machines to interlock handling and appropriate contingency measures like beam dump scenarios. The FAIR facility will employ WhiteRabbit, a time based system which delivers an instruction and a corresponding execution time to a machine. In order to meet the deadlines in any given production chain, instructions need to be sent out ahead of time. For this purpose, code execution and message delivery times need to be known in advance. The FAIR Timing Master needs to be reliably capable of satisfying these timing requirements as well as being fault tolerant. Event sequences of recorded production chains indicate that low reaction times to internal and external events and fast, parallel execution are required. This suggests a slim architecture, especially devised for this purpose. Using the thread model of an OS or other high level programs on a generic CPU would be counterproductive when trying to achieve deterministic processing times. This paper deals with the analysis of said requirements as well as a comparison of known processor and virtual machine architectures and the possibilities of parallelisation in programmable hardware. In addition, existing proposals at GSI will be checked against these findings. The final goal will be to determine the best instruction set for modelling any given production chain and devising a suitable architecture to execute these models.  
slides icon Slides THCHMUST06 [2.757 MB]  
THDAULT01 Modern System Architectures in Embedded Systems embedded, controls, hardware, software 1260
  • T. Korhonen
    PSI, Villigen, Switzerland
  Several new technologies are making their way also in embedded systems. In addition to FPGA technology which has become commonplace, multicore CPUs and I/O virtualization (among others) are being introduced to the embedded systems. In our paper we present our ideas and studies about how to take advantage of these features in control systems. Some application examples involving things like CPU partitioning, virtualized I/O and so an are discussed, along with some benchmarks.  
slides icon Slides THDAULT01 [1.426 MB]  
THDAULT04 Embedded Linux on FPGA Instruments for Control Interface and Remote Management Linux, embedded, controls, TANGO 1271
  • B.K. Huang, R.M. Myers, R.M. Sharples
    Durham University, Durham, United Kingdom
  • G. Cunningham, G.A. Naylor
    CCFE, Abingdon, Oxon, United Kingdom
  • O. Goudard
    ESRF, Grenoble, France
  • J.J. Harrison
    Merton College, Oxford, United Kingdom
  • R.G.L. Vann
    York University, Heslington, York, United Kingdom
  Funding: This work was part-funded by the RCUK Energy Programme under grant EP/I501045 and the European Communities under the contract of Association between EURATOM and CCFE.
FPGAs are now large enough that they can easily accommodate an embedded 32-bit processor which can be used to great advantage. Running embedded Linux gives the user many more options for interfacing to their FPGA-based instrument, and in some cases this enables removal of the middle-person PC. It is now possible to manage the instrument directly by widely used control systems such EPICS or TANGO. As an example, on MAST (the Mega Amp Spherical Tokamak) at Culham Centre for Fusion Energy, a new vertical feedback system is under development in which waveform coefficients can be changed between plasma discharges to define the plasma position behaviour. Additionally it is possible to use the embedded processor to facilitate remote updating of firmware which, in combination with a watchdog and network booting ensures that full remote management over Ethernet is possible. We also discuss UDP data streaming using embedded Linux and a web based control interface running on the embedded processor to interface to the FPGA board.
slides icon Slides THDAULT04 [2.267 MB]  
THDAULT05 Embedded LLRF Controller with Channel Access on MicroTCA Backplane Interconnect controls, LLRF, EPICS, embedded 1274
  • K. Furukawa, K. Akai, T. Kobayashi, S. Michizono, T. Miura, K. Nakanishi, J.-I. Odagiri
    KEK, Ibaraki, Japan
  • H. Deguchi, K. Hayashi, M. Ryoshi
    Mitsubishi Electric TOKKI Systems, Amagasaki, Hyogo, Japan
  A low-level RF controller has been developed for the accelerator controls for SuperKEKB, Super-conducting RF Test facility (STF) and Compact-ERL (cERL) at KEK. The feedback mechanism will be performed on Vertex-V FPGA with 16-bit ADCs and DACs. The card was designed as an advanced mezzanine card (AMC) for a MicroTCA shelf. An embedded EPICS IOC on the PowerPC core in FPGA will provide the global controls through channel access (CA) protocol on the backplane interconnect of the shelf. No other mechanisms are required for the external linkages. CA is exclusively employed in order to communicate with central controls and with an embedded IOC on a Linux-based PLC for slow controls.  
slides icon Slides THDAULT05 [1.780 MB]  
FRAAUST01 Development of the Machine Protection System for LCLS-I interface, controls, Ethernet, network 1281
  • J.E. Dusatko, M. Boyes, P. Krejcik, S.R. Norum, J.J. Olsen
    SLAC, Menlo Park, California, USA
  Funding: U.S. Department of Energy under Contract Nos. DE-AC02-06CH11357 and DE-AC02-76SF00515
Machine Protection System (MPS) requirements for the Linac Coherent Light Source I demand that fault detection and mitigation occur within one machine pulse (1/120th of a second at full beam rate). The MPS must handle inputs from a variety of sources including loss monitors as well as standard state-type inputs. These sensors exist at various places across the full 2.2km length of the machine. A new MPS has been developed based on a distributed star network where custom-designed local hardware nodes handle sensor inputs and mitigation outputs for localized regions of the LCLS accelerator complex. These Link-Nodes report status information and receive action commands from a centralized processor running the MPS algorithm over a private network. The individual Link-Node is a 3u chassis with configurable hardware components that can be setup with digital and analog inputs and outputs, depending upon the sensor and actuator requirements. Features include a custom MPS digital input/output subsystem, a private Ethernet interface, an embedded processor, a custom MPS engine implemented in an FPGA and an Industry Pack (IP) bus interface, allowing COTS and custom analog/digital I/O modules to be utilized for MPS functions. These features, while capable of handing standard MPS state-type inputs and outputs, allow other systems like beam loss monitors to be completely integrated within them. To date, four different types of Link-Nodes are in use in LCLS-I. This paper describes the design, construction and implementation of the LCLS MPS with a focus in the Link-Node.
slides icon Slides FRAAUST01 [3.573 MB]