Keyword: LLRF
Paper Title Other Keywords Page
MOPMN016 The Spiral2 Radiofrequency Command Control controls, interface, cavity, EPICS 274
  • D.T. Touchard, C. Berthe, P. Gillette, M. Lechartier, E. Lécorché, G. Normand
    GANIL, Caen, France
  • Y. Lussignol, D. Uriot
    CEA/DSM/IRFU, France
  Mainly for carrying out nuclear physics experiences, the SPIRAL2 facility based at Caen in France will aim to provide new radioactive rare ion or high intensity stable ion beams. The driver accelerator uses several radiofrequency systems: RFQ, buncher and superconducting cavities, driven by independent amplifiers and controlled by digital electronics. This low level radiofrequency subsystem is integrated into a regulated loop driven by the control system. A test of a whole system is foreseen to define and check the computer control interface and applications. This paper describes the interfaces to the different RF equipment into the EPICS based computer control system. CSS supervision and foreseen high level tuning XAL/JAVA based applications are also considered.  
poster icon Poster MOPMN016 [0.986 MB]  
MOPMS009 IFMIF LLRF Control System Architecture Based on Epics EPICS, controls, interface, database 339
  • J.C. Calvo, A. Ibarra, A. Salom
    CIEMAT, Madrid, Spain
  • M.A. Patricio
    UCM, Colmenarejo, Spain
  • M.L. Rivers
    ANL, Argonne, USA
  The IFMIF-EVEDA (International Fusion Materials Irradiation Facility - Engineering Validation and Engineering Design Activity) linear accelerator will be a 9 MeV, 125mA CW (Continuous Wave) deuteron accelerator prototype to validate the technical options of the accelerator design for IFMIF. The RF (Radio Frequency) power system of IFMIF-EVEDA consists of 18 RF chains working at 175MHz with three amplification stages each; each one of the required chains for the accelerator prototype is based on several 175MHz amplification stages. The LLRF system provides the RF Drive input of the RF plants. It controls the amplitude and phase of this signal to be synchronized with the beam and it also controls the resonance frequency of the cavities. The system is based on a commercial cPCI FPGA Board provided by Lyrtech and controlled by a Windows Host PC. For this purpose, it is mandatory to communicate the cPCI FPGA Board with an EPICS Channel Access, building an IOC (Input Output Controller) between Lyrtech board and EPICS. A new software architecture to design a device support, using AsynPortDriver class and CSS as a GUI (Graphical User Interface), is presented.  
poster icon Poster MOPMS009 [2.763 MB]  
WEBHMUST02 Solid State Direct Drive RF Linac: Control System controls, cavity, experiment, software 638
  • T. Kluge, M. Back, U. Hagen, O. Heid, M. Hergt, T.J.S. Hughes, R. Irsigler, J. Sirtl
    Siemens AG, Erlangen, Germany
  • R. Fleck
    Siemens AG, Corporate Technology, CT T DE HW 4, Erlangen, Germany
  • H.-C. Schröder
    ASTRUM IT GmbH, Erlangen, Germany
  Recently a Solid State Direct Drive ® concept for RF linacs has been introduced [1]. This new approach integrates the RF source, comprised of multiple Silicon Carbide (SiC) solid state Rf-modules [2], directly onto the cavity. Such an approach introduces new challenges for the control of such machines namely the non-linear behavior of the solid state RF-modules and the direct coupling of the RF-modules onto the cavity. In this paper we discuss further results of the experimental program [3,4] to integrate and control 64 RF-modules onto a λ/4 cavity. The next stage of experiments aims on gaining better feed forward control of the system and on detailed system identification. For this purpose a digital control board comprising of a Virtex 6 FPGA, high speed DACs/ADCs and trigger I/O is developed and integrated into the experiment and used to control the system. The design of the board is consequently digital aiming at direct processing of the signals. Power control within the cavity is achieved by an outphasing control of two groups of the RF-modules. This allows a power control without degradation of RF-module efficiency.
[1] Heid O., Hughes T., THPD002, IPAC10, Kyoto, Japan
[2] Irsigler R. et al, 3B-9, PPC11, Chicago IL, USA
[3] Heid O., Hughes T., THP068, LINAC10, Tsukuba, Japan
[4] Heid O., Hughes T., MOPD42, HB2010, Morschach, Switzerland
slides icon Slides WEBHMUST02 [1.201 MB]  
WEPKS010 Architecture Design of the Application Software for the Low-Level RF Control System of the Free-Electron Laser at Hamburg controls, software, cavity, interface 798
  • Z. Geng
    SLAC, Menlo Park, California, USA
  • V. Ayvazyan
    DESY, Hamburg, Germany
  • S. Simrock
    ITER Organization, St. Paul lez Durance, France
  The superconducting linear accelerator of the Free-Electron Laser at Hamburg (FLASH) provides high performance electron beams to the lasing system to generate synchrotron radiation to various users. The Low-Level RF (LLRF) system is used to maintain the beam stabilities by stabilizing the RF field in the superconducting cavities with feedback and feed forward algorithms. The LLRF applications are sets of software to perform RF system model identification, control parameters optimization, exception detection and handling, so as to improve the precision, robustness and operability of the LLRF system. In order to implement the LLRF applications in the hardware with multiple distributed processors, an optimized architecture of the software is required for good understandability, maintainability and extendibility. This paper presents the design of the LLRF application software architecture based on the software engineering approach and the implementation at FLASH.  
poster icon Poster WEPKS010 [0.307 MB]  
THDAULT05 Embedded LLRF Controller with Channel Access on MicroTCA Backplane Interconnect controls, EPICS, embedded, FPGA 1274
  • K. Furukawa, K. Akai, T. Kobayashi, S. Michizono, T. Miura, K. Nakanishi, J.-I. Odagiri
    KEK, Ibaraki, Japan
  • H. Deguchi, K. Hayashi, M. Ryoshi
    Mitsubishi Electric TOKKI Systems, Amagasaki, Hyogo, Japan
  A low-level RF controller has been developed for the accelerator controls for SuperKEKB, Super-conducting RF Test facility (STF) and Compact-ERL (cERL) at KEK. The feedback mechanism will be performed on Vertex-V FPGA with 16-bit ADCs and DACs. The card was designed as an advanced mezzanine card (AMC) for a MicroTCA shelf. An embedded EPICS IOC on the PowerPC core in FPGA will provide the global controls through channel access (CA) protocol on the backplane interconnect of the shelf. No other mechanisms are required for the external linkages. CA is exclusively employed in order to communicate with central controls and with an embedded IOC on a Linux-based PLC for slow controls.  
slides icon Slides THDAULT05 [1.780 MB]