Keyword: Ethernet
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TUBAUST02 FPGA Communications Based on Gigabit Ethernet FPGA, interface, hardware, controls 547
  • L.R. Doolittle, C. Serrano
    LBNL, Berkeley, California, USA
  The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and affordability. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip- and board-independent FPGA design which implements the Gigabit Ethernet standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer.  
slides icon Slides TUBAUST02 [0.909 MB]  
WEBHMULT03 EtherBone - A Network Layer for the Wishbone SoC Bus operation, hardware, software, timing 642
  • M. Kreider, W.W. Terpstra
    GSI, Darmstadt, Germany
  • J.H. Lewis, J. Serrano, T. Włostowski
    CERN, Geneva, Switzerland
  Today, there are several System on a Chip (SoC) bus systems. Typically, these busses are confined on-chip and rely on higher level components to communicate with the outside world. Taking these systems a step further, we see the possibility of extending the reach of the SoC bus to remote FPGAs or processors. This leads to the idea of the EtherBone (EB) core, which connects a Wishbone (WB) Ver. 4 Bus via a Gigabit Ethernet based network link to remote peripheral devices. EB acts as a transparent interconnect module towards attached WB Bus devices. Address information and data from one or more WB bus cycles is preceded with a descriptive header and encapsulated in a UDP/IP packet. Because of this standard compliance, EB is able to traverse Wide Area Networks and is therefore not bound to a geographic location. Due to the low level nature of the WB bus, EB provides a sound basis for remote hardware tools like a JTAG debugger, In-System-Programmer (ISP), boundary scan interface or logic analyser module. EB was developed in the scope of the WhiteRabbit Timing Project (WR) at CERN and GSI/FAIR, which employs GigaBit Ethernet technology to communicate with memory mapped slave devices. WR will make use of EB as means to issue commands to its timing nodes and control connected accelerator hardware.  
slides icon Slides WEBHMULT03 [1.547 MB]  
WEBHMULT04 Sub-nanosecond Timing System Design and Development for LHAASO Project detector, timing, network, FPGA 646
  • G.H. Gong, S. Chen, Q. Du, J.M. Li, Y. Liu
    Tsinghua University, Beijing, People's Republic of China
  • H. He
    IHEP Beijing, Beijing, People's Republic of China
  Funding: National Science Foundation of China (No.11005065)
The Large High Altitude Air Shower Observatory (LHAASO) [1] project is designed to trace galactic cosmic ray sources by approximately 10,000 different types of ground air shower detectors. Reconstruction of cosmic ray arrival directions requires sub-nanosecond time synchronization, a novel design of the LHAASO timing system by means of packet-based frequency distribution and time synchronization over Ethernet is proposed. The White Rabbit Protocol (WR) [2] is applied as the infrastructure of the timing system, which implements a distributed adaptive phase tracking technology based on Synchronous Ethernet to lock all local clocks, and a real time delay calibration method based on the Precision Time Protocol to keep all local time synchronized within a nanosecond. We also demonstrate the development and test status on prototype WR switches and nodes.
[1] Cao Zhen, "A future project at tibet: the large high altitude air shower observatory (LHAASO)", Chinese Phys. C 34 249,2010
[2] P. Moreira, et al, "White Rabbit: Sub-Nanosecond Timing Distribution over Ethernet", ISPCS 2009
slides icon Slides WEBHMULT04 [8.775 MB]  
WEMAU004 Integrating EtherCAT Based IO into EPICS at Diamond EPICS, controls, real-time, Linux 662
  • R. Mercado, I.J. Gillingham, J. Rowland, K.G. Wilkinson
    Diamond, Oxfordshire, United Kingdom
  Diamond Light Source is actively investigating the use of EtherCAT-based Remote I/O modules for the next phase of photon beamline construction. Ethernet-based I/O in general is attractive, because of reduced equipment footprint, flexible configuration and reduced cabling. EtherCAT offers, in addition, the possibility of using inexpensive Ethernet hardware, off-the-shelf components with a throughput comparable to current VME based solutions. This paper presents the work to integrate EtherCAT-based I/O to the EPICS control system, listing platform decisions, requirement considerations and software design, and discussing the use of real-time pre-emptive Linux extensions to support high-rate devices that require deterministic sampling.  
slides icon Slides WEMAU004 [0.057 MB]  
poster icon Poster WEMAU004 [0.925 MB]  
WEMMU007 Reliability in a White Rabbit Network network, timing, controls, hardware 698
  • M. Lipiński, J. Serrano, T. Włostowski
    CERN, Geneva, Switzerland
  • C. Prados
    GSI, Darmstadt, Germany
  White Rabbit (WR) is a time-deterministic, low-latency Ethernet-based network which enables transparent, sub-ns accuracy timing distribution. It is being developed to replace the General Machine Timing (GMT) system currently used at CERN and will become the foundation for the control system of the Facility for Antiproton and Ion Research (FAIR) at GSI. High reliability is an important issue in WR's design, since unavailability of the accelerator's control system will directly translate into expensive downtime of the machine. A typical WR network is required to lose not more than a single message per year. Due to WR's complexity, the translation of this real-world-requirement into a reliability-requirement constitutes an interesting issue on its own: a WR network is considered functional only if it provides all its services to all its clients at any time. This paper defines reliability in WR and describes how it was addressed by dividing it into sub-domains: deterministic packet delivery, data redundancy, topology redundancy and clock resilience. The studies show that the Mean Time Between Failure (MTBF) of the WR Network is the main factor affecting its reliability. Therefore, probability calculations for different topologies were performed using the "Fault Tree analysis" and analytic estimations. Results of the study show that the requirements of WR are demanding. Design changes might be needed and further in-depth studies required, e.g. Monte Carlo simulations. Therefore, a direction for further investigations is proposed.  
slides icon Slides WEMMU007 [0.689 MB]  
poster icon Poster WEMMU007 [1.080 MB]  
WEPKS009 Integrating Gigabit Ethernet Cameras into EPICS at Diamond Light Source EPICS, controls, software, photon 794
  • T.M. Cobb
    Diamond, Oxfordshire, United Kingdom
  At Diamond Light Source we have selected Gigabit Ethernet cameras supporting GigE Vision for our new photon beamlines. GigE Vision is an interface standard for high speed Ethernet cameras which encourages interoperability between manufacturers. This paper describes the challenges encountered while integrating GigE Vision cameras from a range of vendors into EPICS.  
poster icon Poster WEPKS009 [0.976 MB]  
WEPMN018 Performance Tests of the Standard FAIR Equipment Controller Prototype FPGA, controls, timing, software 919
  • S. Rauch, R. Bär, W. Panschow, M. Thieme
    GSI, Darmstadt, Germany
  For the control system of the new FAIR accelerator facility a standard equipment controller, the Scalable Control Unit (SCU), is presently under development. First prototypes have already been tested in real applications. The controller combines an x86 ComExpress Board and an Altera Arria II FPGA. Over a parallel bus interface called the SCU bus, up to 12 slave boards can be controlled. Communication between CPU and FPGA is done by a PCIe link. We discuss the real time behaviour between the Linux OS and the FPGA Hardware. For the test, a Front-End Software Architecture (FESA) class, running under Linux, communicates with the PCIe bridge in the FPGA. Although we are using PCIe only for single 32 bit wide accesses to the FPGA address space, the performance still seems sufficient. The tests showed an average response time to IRQs of 50 microseconds with a 1.6 GHz Intel Atom CPU. This includes the context change to the FESA userspace application and the reply back to the FPGA. Further topics are the bandwidth of the PCIe link for single/burst transfers and the performance of the SCU bus communication.  
WEPMN024 NSLS-II Beam Position Monitor Embedded Processor and Control System embedded, controls, EPICS, FPGA 932
  • K. Ha, L.R. Dalesio, J.H. De Long, J. Mead, Y. Tian, K. Vetter
    BNL, Upton, New York, USA
  Funding: Work supported by DOE contract No: DE-AC02-98CH10886
NSLS-II is a 3 Gev 3rd generation light source that is currently under construction. A sub-micron Digital Beam Position Monitor (DBPM) system which is hardware electronics and embedded software processor and EPICS IOC has been successfully developed and tested in the ALS storage ring and BNL Lab.
WEPMN026 Evolution of the CERN Power Converter Function Generator/Controller for Operation in Fast Cycling Accelerators controls, network, software, radiation 939
  • D.O. Calcoen, Q. King, P.F. Semanaz
    CERN, Geneva, Switzerland
  Power converters in the LHC are controlled by the second generation of an embedded computer known as a Function Generator/Controller (FGC2). Following the success of this control system, new power converter installations at CERN will be based around an evolution of the design - a third generation called FGC3. The FGC3 will initially be used in the PS Booster and Linac4. This paper compares the hardware of the two generations of FGC and details the decisions made during the design of the FGC3.  
poster icon Poster WEPMN026 [0.586 MB]  
WEPMN030 Power Supply Control Interface for the Taiwan Photon Source power-supply, controls, interface, quadrupole 950
  • C.Y. Wu, J. Chen, Y.-S. Cheng, P.C. Chiu, K.T. Hsu, K.H. Hu, C.H. Kuo, D. Lee, C.Y. Liao, K.-B. Liu
    NSRRC, Hsinchu, Taiwan
  The Taiwan Photon Source (TPS) is a latest generation synchrotron light source. Stringent power supply specifications should be met to achieve design goals of the TPS. High precision power supply equipped with 20, 18, and 16 bits DAC for the storage ring dipole, quadrupole, and sextupole are equipped with Ethernet interfaces. Control interface include basic functionality and some advanced features which are useful for performance monitoring and post-mortem diagnostics. Power supply of these categories can be accessed by EPICS IOCs. The corrector power supplies' control interface is a specially designed embedded interface module which will be mounted on the corrector power supply cages to achieve required performance. The setting reference of the corrector power supply is generated by 20 bits DAC and readback is done by 24 bits ADC. The interface module has embedded EPICS IOC for slow control. Fast setting ports are also supported by the internal FPGA for orbit feedback supports.  
WEPMS017 The Global Trigger Processor: A VXS Switch Module for Triggering Large Scale Data Acquisition Systems FPGA, interface, hardware, embedded 1010
  • S.R. Kaneta, C. Cuevas, H. Dong, W. Gu, E. Jastrzembski, N. Nganga, B.J. Raydo, J. Wilson
    JLAB, Newport News, Virginia, USA
  Funding: Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177.
The 12 GeV upgrade for Jefferson Lab's Continuous Electron Beam Accelerator Facility requires the development of a new data acquisition system to accommodate the proposed 200 kHz Level 1 trigger rates expected for fixed target experiments at 12 GeV. As part of a suite of trigger electronics comprised of VXS switch and payload modules, the Global Trigger Processor (GTP) will handle up to 32,768 channels of preprocessed trigger information data from the multiple detector systems that surround the beam target at a system clock rate of 250 MHz. The GTP is configured with user programmable Physics trigger equations and when trigger conditions are satisfied, the GTP will activate the storage of data for subsequent analysis. The GTP features an Altera Stratix IV GX FPGA allowing interface to 16 Sub-System Processor modules via 32 5-Gbps links, DDR2 and flash memory devices, two gigabit Ethernet interfaces using Nios II embedded processors, fiber optic transceivers, and trigger output signals. The GTP's high-bandwidth interconnect with the payload modules in the VXS crate, the Ethernet interface for parameter control, status monitoring, and remote update, and the inherent nature of its FPGA give it the flexibility to be used large variety of tasks and adapt to future needs. This paper details the responsibilities of the GTP, the hardware's role in meeting those requirements, and elements of the VXS architecture that facilitated the design of the trigger system. Also presented will be the current status of development including significant milestones and challenges.
poster icon Poster WEPMS017 [0.851 MB]  
WEPMS024 ALBA High Voltage Splitter - Power Distribution to Ion Pumps ion, high-voltage, controls, vacuum 1028
  • J.J. Jamroz, E. Al-dmour, D.B. Beltrán, J. Klora, R. Martin, O. Matilla, S. Rubio-Manrique
    CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain
  High Voltage Splitter (HVS) is an equipment designed in Alba that allows a high voltage (HV) distribution (up to +7kV) from one ion pump controller up to eight ion pumps. Using it, the total number of high voltage power supplies needed in Alba's vacuum installation has decreased significantly. The current drawn by each splitter channel is measured independently inside a range from 10nA up to 10mA with 5% accuracy, those measurements are a base for vacuum pressure calculations. A relation, current-pressure depends mostly on the ion pump type, so different tools providing the full calibration flexibility have been implemented. Splitter settings, status and recorded data are accessible over a 10/100 Base-T Ethernet network, none the less a local (manual) control was implemented mostly for service purposes. The device supports also additional functions as a HV cable interlock, pressure interlock output cooperating with the facility's Equipment Protection System (EPS), programmable pressure warnings/alarms and automatic calibration process based on an external current source. This paper describes the project, functionality, implementation, installation and operation as a part of the vacuum system at Alba.  
poster icon Poster WEPMS024 [3.734 MB]  
WEPMS025 Low Current Measurements at ALBA controls, data-acquisition, diagnostics, TANGO 1032
  • J. Lidón-Simon, D.F.C. Fernández-Carreiras, J.V. Gigante, J.J. Jamroz, J. Klora, O. Matilla
    CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain
  High accuracy low current readout is an extensively demanded technique in 3rd generation synchrotrons. Whether reading from scintillation excited large-area photodiodes for beam position measurement or out of gold meshes or metallic coated surfaces in drain-current based intensity monitors, low current measurement devices are an ubiquitous need both for diagnostics and data acquisition in today's photon labs. In order to tackle the problem of measuring from various sources of different nature and magnitude synchronously, while remaining flexible at the same time, ALBA has developed a 4 independent channel electrometer. It is based on transimpedance amplifiers and integrates high resolution ADC converters and an 10/100 Base-T Ethernet communication port. Each channel has independently configurable range, offset and low pass filter cut-off frequency settings and the main unit has external I/O to synchronize the data acquisition with the rest of the control system.  
poster icon Poster WEPMS025 [0.797 MB]  
WEPMS027 The RF Control System of the SSRF 150MeV Linac controls, interface, linac, EPICS 1039
  • S.M. Hu, J.G. Ding, G.-Y. Jiang, L.R. Shen, M.H. Zhao, S.P. Zhong
    SINAP, Shanghai, People's Republic of China
  Shanghai Synchrotron Radiation Facility (SSRF) use a 150 MeV linear electron accelerator as injector, its RF system consists of many discrete devices. The control system is mainly composed of a VME controller and a home-made signal conditioner with DC power supplies. The uniform signal conditioner serves as a hardware interface between the controller and the RF components. The DC power supplies are used for driving the mechanical phase shifters. The control software is based on EPICS toolkit. Device drivers and related runtime database for the VME modules were developed. The operator interface was implemented by EDM.  
poster icon Poster WEPMS027 [0.702 MB]  
WEPMU034 Infrastructure of Taiwan Photon Source Control Network controls, network, EPICS, timing 1145
  • Y.-T. Chang, J. Chen, Y.-S. Cheng, K.T. Hsu, S.Y. Hsu, K.H. Hu, C.H. Kuo, C.Y. Wu
    NSRRC, Hsinchu, Taiwan
  A reliable, flexible and secure network is essential for the Taiwan Photon Source (TPS) control system which is based upon the EPICS toolkit framework. Subsystem subnets will connect to control system via EPICS based CA gateways for forwarding data and reducing network traffic. Combining cyber security technologies such as firewall, NAT and VLAN, control network is isolated to protect IOCs and accelerator components. Network management tools are used to improve network performance. Remote access mechanism will be constructed for maintenance and troubleshooting. The Ethernet is also used as fieldbus for instruments such as power supplies. This paper will describe the system architecture for the TPS control network. Cabling topology, redundancy and maintainability are also discussed.  
THDAUST03 The FERMI@Elettra Distributed Real-time Framework real-time, Linux, controls, network 1267
  • L. Pivetta, G. Gaio, R. Passuello, G. Scalamera
    ELETTRA, Basovizza, Italy
  Funding: The work was supported in part by the Italian Ministry of University and Research under grants FIRB-RBAP045JF2 and FIRB-RBAP06AWK3
FERMI@Elettra is a Free Electron Laser (FEL) based on a 1.5 GeV linac. The pulsed operation of the accelerator and the necessity to characterize and control each electron bunch requires synchronous acquisition of the beam diagnostics together with the ability to drive actuators in real-time at the linac repetition rate. The Adeos/Xenomai real-time extensions have been adopted in order to add real-time capabilities to the Linux based control system computers running the Tango software. A software communication protocol based on gigabit Ethernet and known as Network Reflective Memory (NRM) has been developed to implement a shared memory across the whole control system, allowing computers to communicate in real-time. The NRM architecture, the real-time performance and the integration in the control system are described.
slides icon Slides THDAUST03 [0.490 MB]  
FRAAUST01 Development of the Machine Protection System for LCLS-I interface, controls, FPGA, network 1281
  • J.E. Dusatko, M. Boyes, P. Krejcik, S.R. Norum, J.J. Olsen
    SLAC, Menlo Park, California, USA
  Funding: U.S. Department of Energy under Contract Nos. DE-AC02-06CH11357 and DE-AC02-76SF00515
Machine Protection System (MPS) requirements for the Linac Coherent Light Source I demand that fault detection and mitigation occur within one machine pulse (1/120th of a second at full beam rate). The MPS must handle inputs from a variety of sources including loss monitors as well as standard state-type inputs. These sensors exist at various places across the full 2.2km length of the machine. A new MPS has been developed based on a distributed star network where custom-designed local hardware nodes handle sensor inputs and mitigation outputs for localized regions of the LCLS accelerator complex. These Link-Nodes report status information and receive action commands from a centralized processor running the MPS algorithm over a private network. The individual Link-Node is a 3u chassis with configurable hardware components that can be setup with digital and analog inputs and outputs, depending upon the sensor and actuator requirements. Features include a custom MPS digital input/output subsystem, a private Ethernet interface, an embedded processor, a custom MPS engine implemented in an FPGA and an Industry Pack (IP) bus interface, allowing COTS and custom analog/digital I/O modules to be utilized for MPS functions. These features, while capable of handing standard MPS state-type inputs and outputs, allow other systems like beam loss monitors to be completely integrated within them. To date, four different types of Link-Nodes are in use in LCLS-I. This paper describes the design, construction and implementation of the LCLS MPS with a focus in the Link-Node.
slides icon Slides FRAAUST01 [3.573 MB]  
FRBHAULT04 Commissioning of the FERMI@Elettra Fast Trajectory Feedback feedback, controls, real-time, linac 1314
  • G. Gaio, M. Lonza, R. Passuello, L. Pivetta, G. Strangolino
    ELETTRA, Basovizza, Italy
  Funding: The work was supported in part by the Italian Ministry of University and Research under grants FIRB-RBAP045JF2 and FIRB-RBAP06AWK3
FERMI@Elettra is a new 4th-generation light source based on a single pass Free Electron Laser (FEL). In order to ensure the feasibility of the free electron lasing and the quality of the produced photon beam, a high degree of stability is required for the main parameters of the electron beam. For this reason a flexible real-time feedback framework integrated in the control system has been developed. The first implemented bunch-by-bunch feedback loop controls the beam trajectory. The measurements of the beam position and the corrector magnet settings are synchronized to the 50 Hz linac repetition rate by means of the real-time framework. The feedback system implementation, the control algorithms and preliminary close loop results are presented.
slides icon Slides FRBHAULT04 [2.864 MB]  
FRCAUST02 Status of the CSNS Controls System controls, interface, linac, power-supply 1341
  • C.H. Wang
    IHEP Beijing, Beijing, People's Republic of China
  The China Spallation Neutron Source (CSNS) is planning to start construction in 2011 in China. The CSNS controls system will use EPICS as development platform. The scope of the controls system covers thousands of devices located in Linac, RCS and two transfer lines. The interface from the control system to the equipment will be through VME Power PC processors and embedded PLC as well as embedded IPC. The high level applications will choose XAL core and Eclipse platform. Oracle database is used to save historical data. This paper introduces controls preliminary design and progress. Some key technologies, prototypes,schedule and personnel plan are also discussed.  
slides icon Slides FRCAUST02 [3.676 MB]