ICALEPCS2013 - List of Keywords (FPGA)

Paper	Title	Other Keywords	Page
MOPPC025	A Movement Control System for Roman Pots at the LHC	controls, collimation, interface, experiment	115
	B. Farnham, O.O. Andreassen, I. Atanassov, J. Baechler, B. Copy, M. Deile, M. Dutour, P. Fassnacht, S. Franz, S. Jakobsen, F. Lucas Rodríguez, X. Pons, E. Radermacher, S. Ravat, F. Ravotti, S. Redaelli CERN, Geneva, Switzerland K.H. Hiller DESY Zeuthen, Zeuthen, Germany
	This paper describes the movement control system for detector positioning based on the Roman Pot design used by the ATLAS-ALFA and TOTEM experiments at the LHC. A key system requirement is that LHC machine protection rules are obeyed: the position is surveyed every 20ms with an accuracy of 15?m. If the detectors move too close to the beam (outside limits set by LHC Operators) the LHC interlock system is triggered to dump the beam. LHC Operators in the CERN Control Centre (CCC) drive the system via an HMI provided by a custom built Java application which uses Common Middleware (CMW) to interact with lower level components. Low-level motorization control is executed using National Instruments PXI devices. The DIM protocol provides the software interface to the PXI layer. A FESA gateway server provides a communication bridge between CMW and DIM. A cut down laboratory version of the system was built to provide a platform for verifying the integrity of the full chain, with respect to user and machine protection requirements, and validating new functionality before deploying to the LHC. The paper contains a detailed system description, test bench results and foreseen system improvements.

MOPPC028	High-Density Power Converter Real-Time Control for the MedAustron Synchrotron	controls, timing, operation, real-time	127
	J. Gutleber, A.B. Brett, M. Hager, J. Junuzovic, M. Junuzovic, M. Marchhart, R. Moser, H. Pavetits, C. Torcato de Matos CERN, Geneva, Switzerland A. Ambrosch, A.B. Brett, P. Fraboulet, M. Hager, J. Junuzovic, M. Junuzovic, M. Marchhart, R. Moser, H. Pavetits, C. Torcato de Matos EBG MedAustron, Wr. Neustadt, Austria J. Dedič, M. Mehle, L. Šepetavc Cosylab, Ljubljana, Slovenia
	The MedAustron accelerator is a synchrotron for light-ion therapy, developed under the guidance of CERN within the MedAustron-CERN collaboration. Procurement of 7 different power converter families and development of the control system were carried out concurrently. Control is optimized for unattended routine clinical operation. Therefore, finding a uniform control solution was paramount to fulfill the ambitious project plan. Another challenge was the need to operate with about 5'000 cycles initially, achieving pipelined operation with pulse-to-pulse re-configuration times smaller than 250 msec. This contribution shows the architecture and design and gives an overview of the system as built and operated. It is based on commercial-off-the-shelf processing hardware at front-end level and on the CERN function generator design at equipment level. The system is self contained, permitting use of parts and the whole is other accelerators. Especially the separation of the power converter from the real-time regulation using CERN's Converter Regulation Board makes this approach an attractive choice for integrating existing power converters in new configurations.
	Poster MOPPC028 [0.892 MB]

MOPPC036	The BPM Integration in the Taiwan Photon Source	booster, storage-ring, feedback, electronics	158
	C.H. Kuo, Y.-T. Chang, J. Chen, Y.-S. Cheng, P.C. Chiu, K.T. Hsu, K.H. Hu, D. Lee, C.Y. Wu NSRRC, Hsinchu, Taiwan
	TPS (Taiwan Photon Source) is a 3 GeV synchrotron light source which is being in construction at NSRRC. The TPS BPM is based on xTCA platform, is used for various request and function reasons. These functions will be discussed. Another purpose is for orbit feedback system. The tradition BPM electronic is separated from orbit feedback system, is just monitor. In the TPS, the orbit feedback system is embedded in the BPM crate with FPGA modules. High throughput backplane, data transfer and processing support rich function for waveform recorder, diagnostic, beam study and transient analysis. The implementation result of the BPM system will be reported in this conference.

MOPPC043	Development of the Thermal Beam Loss Monitors of the Spiral2 Control System	detector, EPICS, controls, monitoring	181
	C.H. Haquin GANIL, Caen, France F. Negoita IFIN, Magurele- Bucuresti, Romania
	The Spiral2 linear accelerator will drive high intensity beams, up to 5mA, to up to 200kW at linac exit. Such beams can seriously damage and activate the machine ! To prevent from such situation, the Machine Protection System (MPS) has been designed. This system is connected to diagnostics indicating if the beam remains under specific limits. As soon as a diagnostic detects its limit is crossed, it informs the MPS which will in turn take actions that can lead to a beam cut-off in appropriated timing requirements. In this process, the Beam Loss Monitors (BLM) are involved in monitoring prompt radiation generated by beam particles interactions with beam line components and responsible for activation, on one side, and thermal effects, on the other side. BLM system relies mainly on scintillator detectors, NIM electronics and a VME subsystem monitoring the heating of the machine. This subsystem, also called «Thermal BLM», will be integrated in the Spiral2 EPICS environment. For its development, a specific project organization has been setup since the development is subcontracted to Cosylab. This paper focuses on the Thermal BLM controls aspects and describes this development process.
	Poster MOPPC043 [0.957 MB]

MOPPC062	Real-Time System Supervision for the LHC Beam Loss Monitoring System at CERN	monitoring, detector, database, operation	242
	C. Zamantzas, B. Dehning, E. Effinger, J. Emery, S. Jackson CERN, Geneva, Switzerland
	The strategy for machine protection and quench prevention of the Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is mainly based on the Beam Loss Monitoring (BLM) system. The LHC BLM system is one of the most complex and large instrumentation systems deployed in the LHC. In addition to protecting the collider, the system also needs to provide a means of diagnosing machine faults and deliver feedback of the losses to the control room as well as to several systems for their setup and analysis. In order to augment the dependability of the system several layers of supervision has been implemented internally and externally to the system. This paper describes the different methods employed to achieve the expected availability and system fault detection.

MOPPC071	Development of the Machine Protection System for FERMILAB'S ASTA Facility	controls, cryomodule, laser, interface	262
	L.R. Carmichael, R. Neswold, A. Warner, J.Y. Wu Fermilab, Batavia, USA
	The Fermilab Advance Superconducting Test Accelerator (ASTA) under development will be capable of delivering an electron beam with up to 3000 bunches per macro-pulse, 5Hz repetition rate and 1.5 GeV beam energy in the final phase. The completed machine will be capable of sustaining an average beam power of 72 KW at the bunch charge of 3.2 nC. A robust Machine Protection System (MPS) capable of interrupting the beam within a macro-pulse and that interfaces well with new and existing controls system infrastructure is being developed to mitigate and analyze faults related to this relatively high damage potential. This paper will describe the component layers of the MPS system, including a FPGA-based Laser Pulse Controller, the Beam Loss Monitoring system design and the controls and related work done to date.
	Poster MOPPC071 [1.479 MB]

MOPPC077	Open Hardware Collaboration: A Way to Improve Efficiency for a Team	detector, hardware, controls, electronics	273
	Y.-M. Abiven, P. Betinelli-Deck, J. Bisou, F. Blache, G. Renaud, S.Z. Zhang SOLEIL, Gif-sur-Yvette, France
	SOLEIL* is a third generation Synchrotron radiation source located near Paris in France. Today, the Storage Ring delivers photon beam to 26 beamlines. In order to improve the machine and beamlines performance, new electronics requirements are identified. For these improvements, up-to-date commercial products are preferred but sometimes custom hardware designs become essential. At SOLEIL, the electronic team (8 people) is in charge of design, implementation and maintenance of 2000 electronics installed for control and data acquisition. This large basement and small team mean there is only little time left to focus on the development of new hardware designs. As alternative, we focus our development on the open Hardware (OHWR) initiative from the CERN dedicated for electronics designers at experimental physics facilities to collaborate on hardware designs. We collaborate as an evaluator and a contributor. We share some boards in the project SPI BOARDS PACKAGE*, developed to face our current challenges. We evaluated TDC core project, and we plan to evaluate FMC carrier. We will present our approach on how to be more efficient with developments, issues to face and the benefit we get. : www.synchrotron-soleil.fr **: www.ohwr.org/projects/spi-board-package

TUMIB07	RASHPA: A Data Acquisition Framework for 2D XRays Detectors	detector, hardware, framework, software	536
	F. Le Mentec, P. Fajardo, C. Herve, A. Homs, T. Le Caer ESRF, Grenoble, France B. Bauvir ITER Organization, St. Paul lez Durance, France
	Funding: Cluster of Research Infrastructures for Synergies in Physics (CRISP) co-funded by the partners and the European Commission under the 7th Framework Programme Grant Agreement 283745 ESRF ESRF research programs, along with the foreseen accelerator sources upgrade, require state-of-the-art instrumentation devices with high data flow acquisition systems. This paper presents RASHPA, a data acquisition framework targeting 2D XRay detectors. By combining a highly configurable multi link PCI Express over cable based data transmission engine and a carefully designed LINUX software stack, RASHPA aims at reaching the performances required by current and future detectors.
	Slides TUMIB07 [0.168 MB]

TUPPC039	Development of a High-speed Diagnostics Package for the 0.2 J, 20 fs, 1 kHz Repetition Rate Laser at ELI Beamlines	laser, diagnostics, controls, interface	646
	J. Naylon, D.K. Kramer ELI-BEAMS, Prague, Czech Republic
	The ELI Beamlines facility aims to provide a selection of high repetition rate terawatt and petawatt femtosecond pulsed lasers, with applications in plasma research, particle acceleration, high-field physics and high intensity extended-UV/X-ray generation. The highest rate laser in the facility will be a 1 kHz femtosecond laser with pulse energy of 200 mJ. This high repetition rate presents unique challenges for the control system, particularly the diagnostics package. This is tasked with measuring key laser parameters such as pulse energy, pointing accuracy, and beam profile. Not only must this system be capable of relaying individual pulse measurements in real-time to the six experimental target chambers, it must also respond with microsecond latency to any aberrations indicating component damage or failure. We discuss the development and testing of a prototype near-field camera profiling system forming part of this diagnostics package consisting of a 1000 fps high resolution camera and FPGA-based beam profile and aberration detection system.
	Poster TUPPC039 [2.244 MB]

TUPPC069	ZEBRA: a Flexible Solution for Controlling Scanning Experiments	detector, EPICS, interface, controls	736
	T.M. Cobb, Y.S. Chernousko, I.S. Uzun Diamond, Oxfordshire, United Kingdom
	This paper presents the ZEBRA product developed at Diamond Light Source. ZEBRA is a stand-alone event handling system with interfaces to multi-standard digital I/O signals (TTL, LVDS, PECL, NIM and Open Collector) and RS422 quadrature incremental encoder signals. Input events can be triggered by input signals, encoder position signals or repetitive time signals, and can be combined using logic gates in an FPGA to generate and output other events. The positions of all 4 encoders can be captured at the time of a given event and made available to the controlling system. All control and status is available through a serial protocol, so there is no dependency on a specific higher level control system. We have found it has applications on virtually all Diamond beamlines, from applications as simple as signal level shifting to, for example, using it for all continuous scanning experiments. The internal functionality is reconfigurable on the fly through the user interface and can be saved to static memory. It provides a flexible solution to interface different third party hardware (detectors and motion controllers) and to configure the required functionality as part of the experiment.
	Poster TUPPC069 [2.909 MB]

TUPPC082	DSP Design Using System Generator	hardware, simulation, booster, interface	770
	J.M. Koch ESRF, Grenoble, France
	When designing a real time control system, a fast data transfer between the different pieces of hardware must be guaranteed since synchronization and determinism have to be respected. One efficient solution to cope with these constraints is to embed the data collection, the signal-processing and the driving of the acting devices in FPGAs. Although this solution imposes that the whole design is being developed for an FPGA, in pure hardware, it is possible to open the part dedicated to the signal processing to non HDL (Hardware Description Language) specialists; the choice has been made here to develop this part under System Generator, in Simulink. Another challenge in such system design is the integration of real time models on already pre-configured hardware platforms. This paper describes with few examples how to interface such hardware with HDL System Generator control systems blocks. The advantages of Simulink for the simulation phase of the design as well as the possibility to introduce models dedicated to the tests are also presented.
	Poster TUPPC082 [0.924 MB]

TUPPC083	FPGA Implementation of a Digital Constant Fraction for Fast Timing Studies in the Picosecond Range	detector, neutron, timing, real-time	774
	P. Mutti, J. Ratel, F. Rey, E. Ruiz-Martinez ILL, Grenoble, France
	Thermal or cold neutron capture on different fission systems is an excellent method to produce a variety of very neutron-rich nuclei. Since neutrons at these energies bring in the reaction just enough energy to produce fission, the fragments remain neutron-rich due to the negligible neutron evaporation thus allowing detailed nuclear structure studies. In 2012 and 2013 a combination of EXOGAM, GASP and Lohengrin germanium detectors has been installed at the PF1B cold neutron beam of the Institut Laue-Langevin. The present paper describes the digital acquisition system used to collect information on all gamma rays emitted by the decaying nuclei. Data have been acquired in a trigger-less mode to preserve a maximum of information for further off-line treatment with a total throughput of about 10 MByte/sec. Special emphasis is devoted to the FPGA implementation of an on-line digital constant fraction algorithm allowing fast timing studies in the pico second range.
	Poster TUPPC083 [9.928 MB]

TUPPC086	Electronics Developments for High Speed Data Throughput and Processing	detector, controls, interface, timing	778
	C. Youngman, B. Fernandes, P. Gessler XFEL. EU, Hamburg, Germany J. Coughlan STFC/RAL, Chilton, Didcot, Oxon, United Kingdom E. Motuk UCL, London, United Kingdom M. Zimmer DESY, Hamburg, Germany
	Funding: The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement No. 283745 The European XFEL DAQ system has to acquire and process data in short bursts every 100ms. Bursts lasts for 600us and contain a maximum of 2700 x-ray pulses with a repetition rate of 4.5MHz which have to be captured and processed before the next burst starts. This time structure defines the boundary conditions for almost all diagnostic and detector related DAQ electronics required and currently being developed for start of operation in fall 2015. Standards used in the electronics developments are: MicroTCA.4 and AdvancedTCA crates, use of FPGAs for data processing, transfer to backend systems via 10Gbps (SFP+) links, and feedback information transfer using 3.125Gbps (SFP) links. Electronics being developed in-house or in collaboration with external institutes and companies include: a Train Builder ATCA blade for assembling and processing data of large-area image detectors, a VETO MTCA.4 development for evaluating pulse information and distributing a trigger decision to detector front-end ASICs and FPGAs with low-latency, a MTCA.4 digitizer module, interface boards for timing and similar synchronization information, etc.
	Poster TUPPC086 [0.983 MB]

TUPPC087	High Level FPGA Programming Framework Based on Simulink	framework, interface, hardware, software	782
	B. Fernandes, P. Gessler, C. Youngman XFEL. EU, Hamburg, Germany
	Funding: The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement No 283745. Modern diagnostic and detector related data acquisition and processing hardware are increasingly being implemented with Field Programmable Gate Array (FPGA) technology. The level of flexibility allows for simpler hardware solutions together with the ability to implement functions during the firmware programming phase. The technology is also becoming more relevant in data processing, allowing for reduction and filtering to be done at the hardware level together with implementation of low-latency feedback systems. However, this flexibility and possibilities require a significant amount of design, programming, simulation and testing work usually done by FPGA experts. A high-level FPGA programming framework is currently under development at the European XFEL in collaboration with the Oxford University within the EU CRISP project. This framework allows for people unfamiliar with FPGA programming to develop and simulate complete algorithms and programs within the MathWorks Simulink graphical tool with real FPGA precision. Modules within the framework allow for simple code reuse by compiling them into libraries, which can be deployed to other boards or FPGAs.
	Poster TUPPC087 [0.813 MB]

TUPPC088	Development of MicroTCA-based Image Processing System at SPring-8	controls, interface, framework, Linux	786
	A. Kiyomichi, M. Masaki, T. Masuda, S. Ueda JASRI/SPring-8, Hyogo-ken, Japan
	In SPring-8, various CCD cameras have been utilized for electron beam diagnostics of accelerators and x-ray imaging experiments. PC-based image processing systems are mainly used for the CCD cameras with Cameralink I/F. We have developed a new image processing system based on MicroTCA platform, which has an advantage over PC in robustness and scalability due to its hot-swappable modular architecture. In order to reduce development cost and time, the new system is built with COTS products including a user-configurable Spartan6 AMC with an FMC slot and a Cameralink FMC. The Cameralink FPGA core is newly developed in compliance with the AXI4 open-bus to enhance reusability. The MicroTCA system will be first applied to upgrade of the two-dimensional synchrotron radiation interferometer[1] operating at the SPring-8 storage ring. The sizes and tilt angle of a transverse electron beam profile with elliptical Gaussian distribution are extracted from an observed 2D-interferogram. A dedicated processor AMC (PrAMC) that communicates with the primary PrAMC via backplane is added for fast 2D-fitting calculation to achieve real-time beam profile monitoring during the storage ring operation. [1] "Two-dimensional visible synchrotron light interferometry for transverse beam-profile measurement at the SPring-8 storage ring", M.Masaki and S.Takano, J. Synchrotron Rad. 10, 295 (2003).
	Poster TUPPC088 [4.372 MB]

TUPPC094	Em# Project. Improvement of Low Current Measurements at Alba Synchrotron	controls, hardware, target, feedback	798
	X. Serra-Gallifa, J.A. Avila-Abellan, J.J. Jamroz, O. Matilla CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain
	After two years with 50 four-channels electrometer measurement units working successfully at Alba beamlines, new features implementation have forced a complete instrument architecture change. This new equipment is taking advantage of the targets achieved as the remarkable low noise in the current amplifier stage and implements new features currently not available in the market. First an embedded 18 bits SAR ADC able to work under up to 500V biasing has been implemented looking for the highest possible accuracy. The data stream is analysed by a flexible data processing based on a FPGA which is able to execute sample-by-sample real-time calculation aimed to be applied in experiments as the current normalization absorption between two channel acquisitions; being able to optimize the SNR of an absorption spectrum. The equipment is oriented from the design stage to be integrated in continuous scans setups, implementing low level timestamp compatible with multiple clock sources standards using an SFP port. This port could also be used in the future to integrate XBPM measures into the FOFB network for the accelerator beam position correction.
	Poster TUPPC094 [0.545 MB]

TUPPC095	Low Cost FFT Scope using LabVIEW cRIO and FPGA	LabView, software, hardware, controls	801
	O.O. Andreassen, L. Arnaudon, I.T. Matasaho, A. Rijllart CERN, Geneva, Switzerland
	At CERN, many digitizers and scopes are starting to age and should be replaced. Much of the equipment is custom made or not available on the market anymore. Replacing this equipment with the equivalent of today would either be time consuming or expensive. This paper looks at the pros and cons of using COTS systems like NI-cRIO and NI-PXIe and their FPGA capabilities as flexible instruments, replacing costly spectrum analyzers and older scopes. It adds some insight on what had to be done to integrate and deploy the equipment in the unique CERN infrastructure, and the added value of having a fully customizable platform, that makes it possible to stream, store and align the data without any additional equipment.
	Poster TUPPC095 [5.250 MB]

TUPPC098	Advanced Light Source Control System Upgrade – Intelligent Local Controller Replacement	controls, hardware, software, EPICS	809
	W.E. Norum, R.E. Lellinger, G.J. Portmann LBNL, Berkeley, California, USA
	Funding: Work supported by the U.S. Department of Energy under Contract No. DE-AC02-05CH11231 As part of the control system upgrade at the Advanced Light Source (ALS) the existing intelligent local controller (ILC) modules have been replaced. These remote input/output modules provide real-time updates of control setpoints and monitored values. This paper describes the 'ILC Replacement Modules' which have been developed to take on the duties of the existing modules. The new modules use a 100BaseT network connection to communicate with the ALS Experimental Physics and Industrial Control System (EPICS) and are based on a commercial FPGA evaluation board running a microcontroller-like application. In addition to providing remote ana log and digital input/output points the replacement modules also provide some rudimentary logic operations, analog slew rate limiting and accurate time stamping of acquired data. Results of extensive performance testing and experience gained now that the modules have been in service for several months are presented.

TUCOCA01	XFEL Machine Protection System (MPS) Based on uTCA	linac, kicker, operation, undulator	906
	S. Karstensen, M.E. Castro Carballo, J.M. Jäger, M. Staack DESY, Hamburg, Germany
	The European X-Ray Free Electron Laser (XFEL) linear accelerator will provide an electron beam with energies of up to 17.5 GeV and will use it to generate extremely brilliant pulses of spatially coherent xrays. With a designated average beam power of up to 600 kW and beam spot sizes down to few micrometers, the machine will hold a serious damage potential. To ensure safe operation of the accelerator it is necessary to detect dangerous situations by closely monitoring beam losses and the status of critical components. This is the task of the uTCA* based machine protection system (MPS). Many design features of the system have been influenced by experience from existing facilities, particularly the Free Electron Laser in Hamburg (FLASH), which is a kind of 1:10 prototype for the XFEL. A high flexibility of the MPS is essential to guarantee a minimum downtime of the accelerator. The MPS is embedded in the DOOCS** control system. * uTCA: Micro Telecommunications Computing Architecture ** DOOCS: Distributed Object Oriented Control System
	Slides TUCOCA01 [2.255 MB]

TUCOCA09	Klystron Measurement and Protection System for XFEL on the MTCA.4 Architecture	klystron, high-voltage, LLRF, vacuum	937
	Ł. Butkowski, H. Schlarb, V. Vogel DESY, Hamburg, Germany
	The European XFEL free-electron laser is under construction at the DESY. The driving engine of the superconducting accelerator will be 27 RF station. Each of an underground RF station consist from multi beam horizontal klystron which can provide up to 10MW of power at 1.3GHz. The XFEL should work continuously over 20 years with only 1 day per month for maintenance. In order to meet so demanding requirement lifetime of the MBK should be as long as possible. In the real operation the lifetime of tube can be thoroughly reduced by service conditions. To minimize the influence of service conditions to the klystrons lifetime the special fast protection system named as Klystron Lifetime Management System (KLM) has been developed, the main task of this system is to detect all events which can destroy the tube as quickly as possible, and then stop input power to the tube and send signal to stop HV pulse. The tube recovery procedure should depend on the kind of events has happened. KLM is based on the standard LLRF uTCA system for XFEL with additional DC channels. This article gives an overview of implementation of measurement and protection system installed at klystron test stand.
	Slides TUCOCA09 [0.496 MB]

WECOCB01	CERN's FMC Kit	hardware, controls, interface, feedback	1020
	E. Van der Bij, M. Cattin, E. Gousiou, J. Serrano, T. Włostowski CERN, Geneva, Switzerland
	In the frame of the renovation of controls and data acquisition electronics for accelerators, the BE-CO-HT section at CERN has designed a kit based on carriers and mezzanines following the FPGA Mezzanine Card (FMC, VITA 57) standard. Carriers exist in VME64x and PCIe form factors, with a PXIe carrier underway. Mezzanines include an Analog to Digital Converter (ADC), a Time to Digital Converter (TDC) and a fine delay generator. All of the designs are licensed under the CERN Open Hardware Licence (OHL) and commercialized by companies. The paper discusses the benefits of this carrier-mezzanine strategy and of the Open Hardware based commercial paradigm, along with performance figures and plans for the future.
	Slides WECOCB01 [3.300 MB]

WECOCB03	Development of a Front-end Data-Acquisition System with a Camera Link FMC for High-Bandwidth X-Ray Imaging Detectors	detector, interface, experiment, synchrotron	1028
	C. Saji, T. Ohata, T. Sugimoto, R. Tanaka, M. Yamaga JASRI/SPring-8, Hyogo-ken, Japan T. Abe RIKEN SPring-8 Center, Innovative Light Sources Division, Hyogo, Japan T. Kudo RIKEN SPring-8 Center, Sayo-cho, Sayo-gun, Hyogo, Japan
	X-ray imaging detectors are indispensable for synchrotron radiation experiments and growing up with larger number of pixels and higher frame rate to acquire more information on the samples. The novel detector with data rate of up to 8 Gbps/sensor, SOPHIAS, is under development at SACLA facility. Therefore, we have developed a new front-end DAQ system with high data rate beyond the present level. The system consists of an FPGA-based evaluation board and a FPGA mezzanine card (FMC). As the FPGA interface, FMC was adopted for supporting variety of interfaces and considering COTS system. Since the data transmission performance of the FPGA board in combination with the FMCs was already evaluated as about 20 Gbps between boards, our choice of devices has the potential to meet the requirements of SOPHIAS detector. We made a FMC with Camera Link (CL) interface to support 1st phase of SOPHIAS detector. Since almost CL configurations are supported, the system handles various types of commercial cameras as well as new detector. Moreover, the FMC has general purpose input/output to satisfy various experimental requirements. We report the design of new front-end DAQ and results of evaluation. A Study of a Prototype DAQ System with over 10 Gbps Bandwidth for the SACLA X-Ray Experiments, C. Saji, T. Ohata, T. Sugimoto, R. Tanaka, and M. Yamaga, 2012 IEEE NSS and MIC, p.1619-p.1622
	Slides WECOCB03 [0.980 MB]

WECOCB05	Modern Technology in Disguise	controls, software, interface, hardware	1032
	T. Korhonen, D. Anicic, B. Kalantari, R. Kalt, M.P. Laznovsky, T. Schilcher, D. Zimoch PSI, Villigen PSI, Switzerland
	A modern embedded system for fast systems has to incorporate technologies like multicore CPUs, fast serial links and FPGAs for interfaces and local processing. Those technologies are still relatively new and integrating them in a control system infrastructure that either exists already or has to be planned for long-term maintainability is a challenge that needs to be addressed. At PSI we have, in collaboration with an industrial company (IOxOS SA)[], built a board and infrastructure around it solving issues like scalability and modularization of systems that are based on FPGAs and the FMC standard, simplicity in taking such a board in operation and re-using parts of the source code base for FPGA. In addition the board has several state-of-the-art features that are typically found in the newer bus systems like MicroTCA, but can still easily be incorporated in our VME64x-based infrastructure. In the presentation we will describe the system architecture, its technical features and how it enables us to effectively develop our different user applications and fast front-end systems. IOxOS SA, Gland, Switzerland, http://www.ioxos ch
	Slides WECOCB05 [0.675 MB]

WECOCB07	Development of an Open-Source Hardware Platform for Sirius BPM and Orbit Feedback	hardware, interface, software, controls	1036
	D.O. Tavares, R.A. Baron, F.H. Cardoso, S.R. Marques, L.M. Russo LNLS, Campinas, Brazil A.P. Byszuk, G. Kasprowicz, A.J. Wojenski Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
	The Brazilian Synchrotron Light Laboratory (LNLS) is developing a BPM and orbit feedback system for Sirius, the new low emmitance synchrotron light source under construction in Brazil. In that context, 3 open-source boards and accompanying low-level firmware/software were developed in cooperation with the Warsaw University of Technology (WUT) to serve as hardware platform for the BPM data acquisition and digital signal processing platform as well as orbit feedback data distributor: (i) FPGA board with 2 high-pin count FMC slots in PICMG AMC form factor; (ii) 4-channel 16-bit 130 MS/s ADC board in ANSI/VITA FMC form factor; (iii) 4-channel 16-bit 250 MS/s ADC board in ANSI/VITA FMC form factor. The experience of integrating the system prototype in a COTS MicroTCA.4 crate will be reported, as well as the planned developments.
	Slides WECOCB07 [4.137 MB]

THPPC060	A PXI-Based Low Level Control for the Fast Pulsed Magnets in the CERN PS Complex	controls, kicker, timing, monitoring	1205
	J. Schipper, E. Carlier, T. Fowler, T. Gharsa CERN, Geneva, Switzerland
	Fast pulsed magnet (kicker) systems are used for beam injection and extraction in the CERN PS complex. A novel approach, based on off-the-shelf PXI components, has been used for the consolidation of the low level part of their control system. Typical functionalities required like interlocking, equipment state control, thyratron drift stabilisation and protection, short circuit detection in magnets and transmission lines, pulsed signal acquisition and fine timing have been successfully integrated within a PXI controller. The controller comprises a National Instruments NI PXI-810x RT real time processor, a multifunctional RIO module including a Virtex-5 LX30 FPGA, a 1 GS/s digitiser and a digital delay module with 1 ns resolution. National Instruments LabVIEW development tools have been used to develop the embedded real time software as well as FPGA configuration and expert application programs. The integration within the CERN controls environment is performed using the Rapid Application Development Environment (RADE) software tools, developed at CERN.
	Poster THPPC060 [0.887 MB]

THPPC067	New EPICS Drivers for Keck TCS Upgrade	EPICS, interface, controls, timing	1231
	J.M. Johnson W.M. Keck Observatory, Kamuela, USA
	Keck Observatory is in the midst of a major telescope control system upgrade. This involves migrating from a VME based EPICS control system originally deployed on Motorola FRC40s VxWorks 5.1 and EPICS R3.13.0Beta12 to a distributed 64-bit X86 Linux servers running RHEL 2.6.33.x and EPICS R3.14.12.x. This upgrade brings a lot of new hardware to the project which includes Ethernet/IP connected PLCs, the ethernet connected DeltaTau Brick controllers, National Instruments MXI RIO, Heidenhain Encoders (and the Heidenhain ethernet connected Encoder Interface Box in particular), Symmetricom PCI based BC635 timing and synchronization cards, and serial line extenders and protocols. Keck has chosen to implement all new drivers using the ASYN framework. This paper will describe the various drivers used in the upgrade including those from the community and those developed by Keck which include BC635, MXI and Heidenhain EIB. It will also discuss the use of the BC635 as a local NTP reference clock and a service for the EPICS general time.

THPPC092	FAIR Timing System Developments Based on White Rabbit	timing, controls, network, interface	1288
	C. Prados, R. Bär, D.H. Beck, J. Hoffmann, M. Kreider, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany M. Kreider Glyndŵr University, Wrexham, United Kingdom
	A new timing system based on White Rabbit (WR) is being developed for the upcoming FAIR facility at GSI, in collaboration with CERN, other institutes and industry partners. The timing system is responsible for the synchronization of nodes with nanosecond accuracy and distribution of timing messages, which allows for real-time control of the accelerator equipment. WR is a fully deterministic Ethernet-based network for general data transfer and synchronization, which is based on Synchronous Ethernet and PTP. The ongoing development at GSI aims for a miniature timing system, which is part of a control system of a proton source, that will be used at one of the accelerators at FAIR. Such a timing system consists of a Data Master generating timing messages, which are forwarded by a WR switch to a handful of timing receiver. The next step is an enhancement of the robustness, reliability and scalability of the system. These features will be integrated in the forthcoming CRYRING control system in GSI. CRYRING serves as a prototype and testing ground for the final control system for FAIR. The contribution presents the overall design and status of the timing system development.
	Poster THPPC092 [0.549 MB]

THPPC115	Fast Orbit Feedback Implementation at Alba Synchrotron	software, real-time, hardware, target	1328
	X. Serra-Gallifa, S. Blanch-Torné, D. Fernández-Carreiras, A. Gutierrez-Milla, Z. Martí, O. Matilla, J. Moldes, A. Olmos, R. Petrocelli CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain
	After the successful accelerator commissioning and with the facility already in operation one of the top short term objectives pointed out by accelerator division was the Fast Orbit Feedback implementation (FOFB). The target of the FOFB system is to hold the electron beam position at submicron range both in vertical and horizontal planes correcting the inestabilities up to 120Hz. This increased beam stability performance is considered a major asset for the beamlines user operation. To achieve this target, the orbit position is acquired from the 88 Libera BPMs at a 10KHz sampling rate, distributed through an independent network and the corrections are calculated and sent to the 176 power supplies that drive the corrector coils. All this correction loop is executed at 10 KHz and the total latency of the system is characterized and minimized optimizing the bandwidth response.
	Poster THPPC115 [0.732 MB]

THPPC125	Evaluation and Implementation of Advanced Process Control with the compactRIO Material of National Instrument	controls, LabView, feedback, real-time	1355
	G. Maire, A. Kehrli, M. Pezzetti, S. Ravat CERN, Geneva, Switzerland B. Charnier, H. Coppier ESIEE, Amiens, France
	Programmable Logic Controller (PLC) is very commonly used in many industries and research applications for process control. However a very complex process control may require algorithms and performances beyond the capability of PLCs, very high-speed or precision controls may also require other solutions. This paper describes recent research conducted to implement advanced process controls with the cRIO material from National Instruments (decoupling of MIMO process control, steady state feedback, observer, Kalman filter, etc). The cRIO systems consist of an embedded real-time controller for communication and processing, a Reconfigurable Field Programmable Array (FPGA) and hot-swappable I/O modules. The paper presents experimental results and the ability of the cRIO to treat complex process control.
	Poster THPPC125 [1.004 MB]

THPPC137	Time Domain Simulation Software of the APS Storage Ring Orbit Real-time Feedback System	feedback, simulation, software, storage-ring	1373
	H. Shang, J. Carwardine, G. Decker, L. Emery, F. Lenkszus, N. Sereno, S. Xu ANL, Argonne, USA
	The APS storage ring real-time feedback (RTFB) system will be upgraded as part of the APS Upgrade project. The time domain simulation software is implemented to find the best parameters of correctors and evaluate the performance of different system configurations. The software includes two parts: the corrector noise model generator and the RTFB simulation. The corrector noise model generates the corrector noise data that are the input for the RTFB simulation. The corrector noise data are generated from the measured APS BPM turn-by-turn noise data, so that simulation actually reproduces the real machine. This paper introduces the algorithm and high-level software development of the corrector noise model generator and the RTFB simulation. Work supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.
	Poster THPPC137 [0.445 MB]

THCOCA02	White Rabbit Status and Prospects	network, distributed, controls, Ethernet	1445
	J. Serrano, G. Daniluk, M.M. Lipiński, E. Van der Bij, T. Włostowski CERN, Geneva, Switzerland D.H. Beck, J. Hoffmann, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany
	The White Rabbit (WR) project started off to provide a sequencing and synchronization solution for the needs of CERN and GSI. Since then, many other users have adopted it to solve problems in the domain of distributed hard real-time systems. The paper discusses the current performance of WR hardware, along with present and foreseen applications. It also describes current efforts to standardize WR under IEEE 1588 and recent developments on reliability of timely data distribution. Then it analyzes the role of companies and the commercial Open Hardware paradigm, finishing with an outline of future plans.
	Slides THCOCA02 [7.955 MB]

FRCOBAB05	Distributed Feedback Loop Implementation in the RHIC Low Level RF Platform	cavity, LLRF, controls, damping	1501
	F. Severino, M. Harvey, T. Hayes, G. Narayan, K.S. Smith BNL, Upton, Long Island, New York, USA
	Funding: Work supported by Brookhaven Science Associates, LLC under Contract No. DEAC02-98CH10886 with the U.S. Department of Energy. We present a brief overview of distributed feedback systems based on the RHIC LLRF Platform. The general architecture and sub-system components of a complex feedback system are described, emphasizing the techniques and features employed to achieve deterministic and low latency data and timing delivery between local and remote sub-systems: processors, FPGA fabric components and the high level control system. In particular, we will describe how we make use of the platform to implement a widely distributed multi-processor and FPGA based longitudinal damping system, which relies on task sharing, tight synchronization and integration to achieve the desired functionality and performance.
	Slides FRCOBAB05 [3.147 MB]

Paper

Title

Other Keywords

Page

MOPPC025

A Movement Control System for Roman Pots at the LHC

controls, collimation, interface, experiment

115

B. Farnham, O.O. Andreassen, I. Atanassov, J. Baechler, B. Copy, M. Deile, M. Dutour, P. Fassnacht, S. Franz, S. Jakobsen, F. Lucas Rodríguez, X. Pons, E. Radermacher, S. Ravat, F. Ravotti, S. Redaelli
CERN, Geneva, Switzerland
K.H. Hiller
DESY Zeuthen, Zeuthen, Germany

This paper describes the movement control system for detector positioning based on the Roman Pot design used by the ATLAS-ALFA and TOTEM experiments at the LHC. A key system requirement is that LHC machine protection rules are obeyed: the position is surveyed every 20ms with an accuracy of 15?m. If the detectors move too close to the beam (outside limits set by LHC Operators) the LHC interlock system is triggered to dump the beam. LHC Operators in the CERN Control Centre (CCC) drive the system via an HMI provided by a custom built Java application which uses Common Middleware (CMW) to interact with lower level components. Low-level motorization control is executed using National Instruments PXI devices. The DIM protocol provides the software interface to the PXI layer. A FESA gateway server provides a communication bridge between CMW and DIM. A cut down laboratory version of the system was built to provide a platform for verifying the integrity of the full chain, with respect to user and machine protection requirements, and validating new functionality before deploying to the LHC. The paper contains a detailed system description, test bench results and foreseen system improvements.

MOPPC028

High-Density Power Converter Real-Time Control for the MedAustron Synchrotron

controls, timing, operation, real-time

127

J. Gutleber, A.B. Brett, M. Hager, J. Junuzovic, M. Junuzovic, M. Marchhart, R. Moser, H. Pavetits, C. Torcato de Matos
CERN, Geneva, Switzerland
A. Ambrosch, A.B. Brett, P. Fraboulet, M. Hager, J. Junuzovic, M. Junuzovic, M. Marchhart, R. Moser, H. Pavetits, C. Torcato de Matos
EBG MedAustron, Wr. Neustadt, Austria
J. Dedič, M. Mehle, L. Šepetavc
Cosylab, Ljubljana, Slovenia

The MedAustron accelerator is a synchrotron for light-ion therapy, developed under the guidance of CERN within the MedAustron-CERN collaboration. Procurement of 7 different power converter families and development of the control system were carried out concurrently. Control is optimized for unattended routine clinical operation. Therefore, finding a uniform control solution was paramount to fulfill the ambitious project plan. Another challenge was the need to operate with about 5'000 cycles initially, achieving pipelined operation with pulse-to-pulse re-configuration times smaller than 250 msec. This contribution shows the architecture and design and gives an overview of the system as built and operated. It is based on commercial-off-the-shelf processing hardware at front-end level and on the CERN function generator design at equipment level. The system is self contained, permitting use of parts and the whole is other accelerators. Especially the separation of the power converter from the real-time regulation using CERN's Converter Regulation Board makes this approach an attractive choice for integrating existing power converters in new configurations.

Poster MOPPC028 [0.892 MB]

MOPPC036

The BPM Integration in the Taiwan Photon Source

booster, storage-ring, feedback, electronics

158

C.H. Kuo, Y.-T. Chang, J. Chen, Y.-S. Cheng, P.C. Chiu, K.T. Hsu, K.H. Hu, D. Lee, C.Y. Wu
NSRRC, Hsinchu, Taiwan

TPS (Taiwan Photon Source) is a 3 GeV synchrotron light source which is being in construction at NSRRC. The TPS BPM is based on xTCA platform, is used for various request and function reasons. These functions will be discussed. Another purpose is for orbit feedback system. The tradition BPM electronic is separated from orbit feedback system, is just monitor. In the TPS, the orbit feedback system is embedded in the BPM crate with FPGA modules. High throughput backplane, data transfer and processing support rich function for waveform recorder, diagnostic, beam study and transient analysis. The implementation result of the BPM system will be reported in this conference.

MOPPC043

Development of the Thermal Beam Loss Monitors of the Spiral2 Control System

detector, EPICS, controls, monitoring

181

C.H. Haquin
GANIL, Caen, France
F. Negoita
IFIN, Magurele- Bucuresti, Romania

The Spiral2 linear accelerator will drive high intensity beams, up to 5mA, to up to 200kW at linac exit. Such beams can seriously damage and activate the machine ! To prevent from such situation, the Machine Protection System (MPS) has been designed. This system is connected to diagnostics indicating if the beam remains under specific limits. As soon as a diagnostic detects its limit is crossed, it informs the MPS which will in turn take actions that can lead to a beam cut-off in appropriated timing requirements. In this process, the Beam Loss Monitors (BLM) are involved in monitoring prompt radiation generated by beam particles interactions with beam line components and responsible for activation, on one side, and thermal effects, on the other side. BLM system relies mainly on scintillator detectors, NIM electronics and a VME subsystem monitoring the heating of the machine. This subsystem, also called «Thermal BLM», will be integrated in the Spiral2 EPICS environment. For its development, a specific project organization has been setup since the development is subcontracted to Cosylab. This paper focuses on the Thermal BLM controls aspects and describes this development process.

Poster MOPPC043 [0.957 MB]

MOPPC062

Real-Time System Supervision for the LHC Beam Loss Monitoring System at CERN

monitoring, detector, database, operation

242

C. Zamantzas, B. Dehning, E. Effinger, J. Emery, S. Jackson
CERN, Geneva, Switzerland

The strategy for machine protection and quench prevention of the Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is mainly based on the Beam Loss Monitoring (BLM) system. The LHC BLM system is one of the most complex and large instrumentation systems deployed in the LHC. In addition to protecting the collider, the system also needs to provide a means of diagnosing machine faults and deliver feedback of the losses to the control room as well as to several systems for their setup and analysis. In order to augment the dependability of the system several layers of supervision has been implemented internally and externally to the system. This paper describes the different methods employed to achieve the expected availability and system fault detection.

MOPPC071

Development of the Machine Protection System for FERMILAB'S ASTA Facility

controls, cryomodule, laser, interface

262

L.R. Carmichael, R. Neswold, A. Warner, J.Y. Wu
Fermilab, Batavia, USA

The Fermilab Advance Superconducting Test Accelerator (ASTA) under development will be capable of delivering an electron beam with up to 3000 bunches per macro-pulse, 5Hz repetition rate and 1.5 GeV beam energy in the final phase. The completed machine will be capable of sustaining an average beam power of 72 KW at the bunch charge of 3.2 nC. A robust Machine Protection System (MPS) capable of interrupting the beam within a macro-pulse and that interfaces well with new and existing controls system infrastructure is being developed to mitigate and analyze faults related to this relatively high damage potential. This paper will describe the component layers of the MPS system, including a FPGA-based Laser Pulse Controller, the Beam Loss Monitoring system design and the controls and related work done to date.

Poster MOPPC071 [1.479 MB]

MOPPC077

Open Hardware Collaboration: A Way to Improve Efficiency for a Team

detector, hardware, controls, electronics

273

Y.-M. Abiven, P. Betinelli-Deck, J. Bisou, F. Blache, G. Renaud, S.Z. Zhang
SOLEIL, Gif-sur-Yvette, France

SOLEIL* is a third generation Synchrotron radiation source located near Paris in France. Today, the Storage Ring delivers photon beam to 26 beamlines. In order to improve the machine and beamlines performance, new electronics requirements are identified. For these improvements, up-to-date commercial products are preferred but sometimes custom hardware designs become essential. At SOLEIL, the electronic team (8 people) is in charge of design, implementation and maintenance of 2000 electronics installed for control and data acquisition. This large basement and small team mean there is only little time left to focus on the development of new hardware designs. As alternative, we focus our development on the open Hardware (OHWR) initiative from the CERN dedicated for electronics designers at experimental physics facilities to collaborate on hardware designs. We collaborate as an evaluator and a contributor. We share some boards in the project SPI BOARDS PACKAGE**, developed to face our current challenges. We evaluated TDC core project, and we plan to evaluate FMC carrier. We will present our approach on how to be more efficient with developments, issues to face and the benefit we get.
*: www.synchrotron-soleil.fr
**: www.ohwr.org/projects/spi-board-package

TUMIB07

RASHPA: A Data Acquisition Framework for 2D XRays Detectors

detector, hardware, framework, software

536

F. Le Mentec, P. Fajardo, C. Herve, A. Homs, T. Le Caer
ESRF, Grenoble, France
B. Bauvir
ITER Organization, St. Paul lez Durance, France

Funding: Cluster of Research Infrastructures for Synergies in Physics (CRISP) co-funded by the partners and the European Commission under the 7th Framework Programme Grant Agreement 283745 ESRF
ESRF research programs, along with the foreseen accelerator sources upgrade, require state-of-the-art instrumentation devices with high data flow acquisition systems. This paper presents RASHPA, a data acquisition framework targeting 2D XRay detectors. By combining a highly configurable multi link PCI Express over cable based data transmission engine and a carefully designed LINUX software stack, RASHPA aims at reaching the performances required by current and future detectors.

Slides TUMIB07 [0.168 MB]

TUPPC039

Development of a High-speed Diagnostics Package for the 0.2 J, 20 fs, 1 kHz Repetition Rate Laser at ELI Beamlines

laser, diagnostics, controls, interface

646

J. Naylon, D.K. Kramer
ELI-BEAMS, Prague, Czech Republic

The ELI Beamlines facility aims to provide a selection of high repetition rate terawatt and petawatt femtosecond pulsed lasers, with applications in plasma research, particle acceleration, high-field physics and high intensity extended-UV/X-ray generation. The highest rate laser in the facility will be a 1 kHz femtosecond laser with pulse energy of 200 mJ. This high repetition rate presents unique challenges for the control system, particularly the diagnostics package. This is tasked with measuring key laser parameters such as pulse energy, pointing accuracy, and beam profile. Not only must this system be capable of relaying individual pulse measurements in real-time to the six experimental target chambers, it must also respond with microsecond latency to any aberrations indicating component damage or failure. We discuss the development and testing of a prototype near-field camera profiling system forming part of this diagnostics package consisting of a 1000 fps high resolution camera and FPGA-based beam profile and aberration detection system.

Poster TUPPC039 [2.244 MB]

TUPPC069

ZEBRA: a Flexible Solution for Controlling Scanning Experiments

detector, EPICS, interface, controls

736

T.M. Cobb, Y.S. Chernousko, I.S. Uzun
Diamond, Oxfordshire, United Kingdom

This paper presents the ZEBRA product developed at Diamond Light Source. ZEBRA is a stand-alone event handling system with interfaces to multi-standard digital I/O signals (TTL, LVDS, PECL, NIM and Open Collector) and RS422 quadrature incremental encoder signals. Input events can be triggered by input signals, encoder position signals or repetitive time signals, and can be combined using logic gates in an FPGA to generate and output other events. The positions of all 4 encoders can be captured at the time of a given event and made available to the controlling system. All control and status is available through a serial protocol, so there is no dependency on a specific higher level control system. We have found it has applications on virtually all Diamond beamlines, from applications as simple as signal level shifting to, for example, using it for all continuous scanning experiments. The internal functionality is reconfigurable on the fly through the user interface and can be saved to static memory. It provides a flexible solution to interface different third party hardware (detectors and motion controllers) and to configure the required functionality as part of the experiment.

Poster TUPPC069 [2.909 MB]

TUPPC082

DSP Design Using System Generator

hardware, simulation, booster, interface

770

J.M. Koch
ESRF, Grenoble, France

When designing a real time control system, a fast data transfer between the different pieces of hardware must be guaranteed since synchronization and determinism have to be respected. One efficient solution to cope with these constraints is to embed the data collection, the signal-processing and the driving of the acting devices in FPGAs. Although this solution imposes that the whole design is being developed for an FPGA, in pure hardware, it is possible to open the part dedicated to the signal processing to non HDL (Hardware Description Language) specialists; the choice has been made here to develop this part under System Generator, in Simulink. Another challenge in such system design is the integration of real time models on already pre-configured hardware platforms. This paper describes with few examples how to interface such hardware with HDL System Generator control systems blocks. The advantages of Simulink for the simulation phase of the design as well as the possibility to introduce models dedicated to the tests are also presented.

Poster TUPPC082 [0.924 MB]

TUPPC083

FPGA Implementation of a Digital Constant Fraction for Fast Timing Studies in the Picosecond Range

detector, neutron, timing, real-time

774

P. Mutti, J. Ratel, F. Rey, E. Ruiz-Martinez
ILL, Grenoble, France

Thermal or cold neutron capture on different fission systems is an excellent method to produce a variety of very neutron-rich nuclei. Since neutrons at these energies bring in the reaction just enough energy to produce fission, the fragments remain neutron-rich due to the negligible neutron evaporation thus allowing detailed nuclear structure studies. In 2012 and 2013 a combination of EXOGAM, GASP and Lohengrin germanium detectors has been installed at the PF1B cold neutron beam of the Institut Laue-Langevin. The present paper describes the digital acquisition system used to collect information on all gamma rays emitted by the decaying nuclei. Data have been acquired in a trigger-less mode to preserve a maximum of information for further off-line treatment with a total throughput of about 10 MByte/sec. Special emphasis is devoted to the FPGA implementation of an on-line digital constant fraction algorithm allowing fast timing studies in the pico second range.

Poster TUPPC083 [9.928 MB]

TUPPC086

Electronics Developments for High Speed Data Throughput and Processing

detector, controls, interface, timing

778

C. Youngman, B. Fernandes, P. Gessler
XFEL. EU, Hamburg, Germany
J. Coughlan
STFC/RAL, Chilton, Didcot, Oxon, United Kingdom
E. Motuk
UCL, London, United Kingdom
M. Zimmer
DESY, Hamburg, Germany

Funding: The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement No. 283745
The European XFEL DAQ system has to acquire and process data in short bursts every 100ms. Bursts lasts for 600us and contain a maximum of 2700 x-ray pulses with a repetition rate of 4.5MHz which have to be captured and processed before the next burst starts. This time structure defines the boundary conditions for almost all diagnostic and detector related DAQ electronics required and currently being developed for start of operation in fall 2015. Standards used in the electronics developments are: MicroTCA.4 and AdvancedTCA crates, use of FPGAs for data processing, transfer to backend systems via 10Gbps (SFP+) links, and feedback information transfer using 3.125Gbps (SFP) links. Electronics being developed in-house or in collaboration with external institutes and companies include: a Train Builder ATCA blade for assembling and processing data of large-area image detectors, a VETO MTCA.4 development for evaluating pulse information and distributing a trigger decision to detector front-end ASICs and FPGAs with low-latency, a MTCA.4 digitizer module, interface boards for timing and similar synchronization information, etc.

Poster TUPPC086 [0.983 MB]

TUPPC087

High Level FPGA Programming Framework Based on Simulink

framework, interface, hardware, software

782

B. Fernandes, P. Gessler, C. Youngman
XFEL. EU, Hamburg, Germany

Funding: The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement No 283745.
Modern diagnostic and detector related data acquisition and processing hardware are increasingly being implemented with Field Programmable Gate Array (FPGA) technology. The level of flexibility allows for simpler hardware solutions together with the ability to implement functions during the firmware programming phase. The technology is also becoming more relevant in data processing, allowing for reduction and filtering to be done at the hardware level together with implementation of low-latency feedback systems. However, this flexibility and possibilities require a significant amount of design, programming, simulation and testing work usually done by FPGA experts. A high-level FPGA programming framework is currently under development at the European XFEL in collaboration with the Oxford University within the EU CRISP project. This framework allows for people unfamiliar with FPGA programming to develop and simulate complete algorithms and programs within the MathWorks Simulink graphical tool with real FPGA precision. Modules within the framework allow for simple code reuse by compiling them into libraries, which can be deployed to other boards or FPGAs.

Poster TUPPC087 [0.813 MB]

TUPPC088

Development of MicroTCA-based Image Processing System at SPring-8

controls, interface, framework, Linux

786

A. Kiyomichi, M. Masaki, T. Masuda, S. Ueda
JASRI/SPring-8, Hyogo-ken, Japan

In SPring-8, various CCD cameras have been utilized for electron beam diagnostics of accelerators and x-ray imaging experiments. PC-based image processing systems are mainly used for the CCD cameras with Cameralink I/F. We have developed a new image processing system based on MicroTCA platform, which has an advantage over PC in robustness and scalability due to its hot-swappable modular architecture. In order to reduce development cost and time, the new system is built with COTS products including a user-configurable Spartan6 AMC with an FMC slot and a Cameralink FMC. The Cameralink FPGA core is newly developed in compliance with the AXI4 open-bus to enhance reusability. The MicroTCA system will be first applied to upgrade of the two-dimensional synchrotron radiation interferometer[1] operating at the SPring-8 storage ring. The sizes and tilt angle of a transverse electron beam profile with elliptical Gaussian distribution are extracted from an observed 2D-interferogram. A dedicated processor AMC (PrAMC) that communicates with the primary PrAMC via backplane is added for fast 2D-fitting calculation to achieve real-time beam profile monitoring during the storage ring operation.
[1] "Two-dimensional visible synchrotron light interferometry for transverse beam-profile measurement at the SPring-8 storage ring", M.Masaki and S.Takano, J. Synchrotron Rad. 10, 295 (2003).

Poster TUPPC088 [4.372 MB]

TUPPC094

Em# Project. Improvement of Low Current Measurements at Alba Synchrotron

controls, hardware, target, feedback

798

X. Serra-Gallifa, J.A. Avila-Abellan, J.J. Jamroz, O. Matilla
CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain

After two years with 50 four-channels electrometer measurement units working successfully at Alba beamlines, new features implementation have forced a complete instrument architecture change. This new equipment is taking advantage of the targets achieved as the remarkable low noise in the current amplifier stage and implements new features currently not available in the market. First an embedded 18 bits SAR ADC able to work under up to 500V biasing has been implemented looking for the highest possible accuracy. The data stream is analysed by a flexible data processing based on a FPGA which is able to execute sample-by-sample real-time calculation aimed to be applied in experiments as the current normalization absorption between two channel acquisitions; being able to optimize the SNR of an absorption spectrum. The equipment is oriented from the design stage to be integrated in continuous scans setups, implementing low level timestamp compatible with multiple clock sources standards using an SFP port. This port could also be used in the future to integrate XBPM measures into the FOFB network for the accelerator beam position correction.

Poster TUPPC094 [0.545 MB]

TUPPC095

Low Cost FFT Scope using LabVIEW cRIO and FPGA

LabView, software, hardware, controls

801

O.O. Andreassen, L. Arnaudon, I.T. Matasaho, A. Rijllart
CERN, Geneva, Switzerland

At CERN, many digitizers and scopes are starting to age and should be replaced. Much of the equipment is custom made or not available on the market anymore. Replacing this equipment with the equivalent of today would either be time consuming or expensive. This paper looks at the pros and cons of using COTS systems like NI-cRIO and NI-PXIe and their FPGA capabilities as flexible instruments, replacing costly spectrum analyzers and older scopes. It adds some insight on what had to be done to integrate and deploy the equipment in the unique CERN infrastructure, and the added value of having a fully customizable platform, that makes it possible to stream, store and align the data without any additional equipment.

Poster TUPPC095 [5.250 MB]

TUPPC098

Advanced Light Source Control System Upgrade – Intelligent Local Controller Replacement

controls, hardware, software, EPICS

809

W.E. Norum, R.E. Lellinger, G.J. Portmann
LBNL, Berkeley, California, USA

Funding: Work supported by the U.S. Department of Energy under Contract No. DE-AC02-05CH11231
As part of the control system upgrade at the Advanced Light Source (ALS) the existing intelligent local controller (ILC) modules have been replaced. These remote input/output modules provide real-time updates of control setpoints and monitored values. This paper describes the 'ILC Replacement Modules' which have been developed to take on the duties of the existing modules. The new modules use a 100BaseT network connection to communicate with the ALS Experimental Physics and Industrial Control System (EPICS) and are based on a commercial FPGA evaluation board running a microcontroller-like application. In addition to providing remote ana log and digital input/output points the replacement modules also provide some rudimentary logic operations, analog slew rate limiting and accurate time stamping of acquired data. Results of extensive performance testing and experience gained now that the modules have been in service for several months are presented.

TUCOCA01

XFEL Machine Protection System (MPS) Based on uTCA

linac, kicker, operation, undulator

906

S. Karstensen, M.E. Castro Carballo, J.M. Jäger, M. Staack
DESY, Hamburg, Germany

The European X-Ray Free Electron Laser (XFEL) linear accelerator will provide an electron beam with energies of up to 17.5 GeV and will use it to generate extremely brilliant pulses of spatially coherent xrays. With a designated average beam power of up to 600 kW and beam spot sizes down to few micrometers, the machine will hold a serious damage potential. To ensure safe operation of the accelerator it is necessary to detect dangerous situations by closely monitoring beam losses and the status of critical components. This is the task of the uTCA* based machine protection system (MPS). Many design features of the system have been influenced by experience from existing facilities, particularly the Free Electron Laser in Hamburg (FLASH), which is a kind of 1:10 prototype for the XFEL. A high flexibility of the MPS is essential to guarantee a minimum downtime of the accelerator. The MPS is embedded in the DOOCS** control system.
* uTCA: Micro Telecommunications Computing Architecture
** DOOCS: Distributed Object Oriented Control System

Slides TUCOCA01 [2.255 MB]

TUCOCA09

Klystron Measurement and Protection System for XFEL on the MTCA.4 Architecture

klystron, high-voltage, LLRF, vacuum

937

Ł. Butkowski, H. Schlarb, V. Vogel
DESY, Hamburg, Germany

The European XFEL free-electron laser is under construction at the DESY. The driving engine of the superconducting accelerator will be 27 RF station. Each of an underground RF station consist from multi beam horizontal klystron which can provide up to 10MW of power at 1.3GHz. The XFEL should work continuously over 20 years with only 1 day per month for maintenance. In order to meet so demanding requirement lifetime of the MBK should be as long as possible. In the real operation the lifetime of tube can be thoroughly reduced by service conditions. To minimize the influence of service conditions to the klystrons lifetime the special fast protection system named as Klystron Lifetime Management System (KLM) has been developed, the main task of this system is to detect all events which can destroy the tube as quickly as possible, and then stop input power to the tube and send signal to stop HV pulse. The tube recovery procedure should depend on the kind of events has happened. KLM is based on the standard LLRF uTCA system for XFEL with additional DC channels. This article gives an overview of implementation of measurement and protection system installed at klystron test stand.

Slides TUCOCA09 [0.496 MB]

WECOCB01

CERN's FMC Kit

hardware, controls, interface, feedback

1020

E. Van der Bij, M. Cattin, E. Gousiou, J. Serrano, T. Włostowski
CERN, Geneva, Switzerland

In the frame of the renovation of controls and data acquisition electronics for accelerators, the BE-CO-HT section at CERN has designed a kit based on carriers and mezzanines following the FPGA Mezzanine Card (FMC, VITA 57) standard. Carriers exist in VME64x and PCIe form factors, with a PXIe carrier underway. Mezzanines include an Analog to Digital Converter (ADC), a Time to Digital Converter (TDC) and a fine delay generator. All of the designs are licensed under the CERN Open Hardware Licence (OHL) and commercialized by companies. The paper discusses the benefits of this carrier-mezzanine strategy and of the Open Hardware based commercial paradigm, along with performance figures and plans for the future.

Slides WECOCB01 [3.300 MB]

WECOCB03

Development of a Front-end Data-Acquisition System with a Camera Link FMC for High-Bandwidth X-Ray Imaging Detectors

detector, interface, experiment, synchrotron

1028

C. Saji, T. Ohata, T. Sugimoto, R. Tanaka, M. Yamaga
JASRI/SPring-8, Hyogo-ken, Japan
T. Abe
RIKEN SPring-8 Center, Innovative Light Sources Division, Hyogo, Japan
T. Kudo
RIKEN SPring-8 Center, Sayo-cho, Sayo-gun, Hyogo, Japan

X-ray imaging detectors are indispensable for synchrotron radiation experiments and growing up with larger number of pixels and higher frame rate to acquire more information on the samples. The novel detector with data rate of up to 8 Gbps/sensor, SOPHIAS, is under development at SACLA facility. Therefore, we have developed a new front-end DAQ system with high data rate beyond the present level. The system consists of an FPGA-based evaluation board and a FPGA mezzanine card (FMC). As the FPGA interface, FMC was adopted for supporting variety of interfaces and considering COTS system. Since the data transmission performance of the FPGA board in combination with the FMCs was already evaluated as about 20 Gbps between boards, our choice of devices has the potential to meet the requirements of SOPHIAS detector*. We made a FMC with Camera Link (CL) interface to support 1st phase of SOPHIAS detector. Since almost CL configurations are supported, the system handles various types of commercial cameras as well as new detector. Moreover, the FMC has general purpose input/output to satisfy various experimental requirements. We report the design of new front-end DAQ and results of evaluation.
* A Study of a Prototype DAQ System with over 10 Gbps Bandwidth for the SACLA X-Ray Experiments, C. Saji, T. Ohata, T. Sugimoto, R. Tanaka, and M. Yamaga, 2012 IEEE NSS and MIC, p.1619-p.1622

Slides WECOCB03 [0.980 MB]

WECOCB05

Modern Technology in Disguise

controls, software, interface, hardware

1032

T. Korhonen, D. Anicic, B. Kalantari, R. Kalt, M.P. Laznovsky, T. Schilcher, D. Zimoch
PSI, Villigen PSI, Switzerland

A modern embedded system for fast systems has to incorporate technologies like multicore CPUs, fast serial links and FPGAs for interfaces and local processing. Those technologies are still relatively new and integrating them in a control system infrastructure that either exists already or has to be planned for long-term maintainability is a challenge that needs to be addressed. At PSI we have, in collaboration with an industrial company (IOxOS SA)[*], built a board and infrastructure around it solving issues like scalability and modularization of systems that are based on FPGAs and the FMC standard, simplicity in taking such a board in operation and re-using parts of the source code base for FPGA. In addition the board has several state-of-the-art features that are typically found in the newer bus systems like MicroTCA, but can still easily be incorporated in our VME64x-based infrastructure. In the presentation we will describe the system architecture, its technical features and how it enables us to effectively develop our different user applications and fast front-end systems.
* IOxOS SA, Gland, Switzerland, http://www.ioxos ch

Slides WECOCB05 [0.675 MB]

WECOCB07

Development of an Open-Source Hardware Platform for Sirius BPM and Orbit Feedback

hardware, interface, software, controls

1036

D.O. Tavares, R.A. Baron, F.H. Cardoso, S.R. Marques, L.M. Russo
LNLS, Campinas, Brazil
A.P. Byszuk, G. Kasprowicz, A.J. Wojenski
Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland

The Brazilian Synchrotron Light Laboratory (LNLS) is developing a BPM and orbit feedback system for Sirius, the new low emmitance synchrotron light source under construction in Brazil. In that context, 3 open-source boards and accompanying low-level firmware/software were developed in cooperation with the Warsaw University of Technology (WUT) to serve as hardware platform for the BPM data acquisition and digital signal processing platform as well as orbit feedback data distributor: (i) FPGA board with 2 high-pin count FMC slots in PICMG AMC form factor; (ii) 4-channel 16-bit 130 MS/s ADC board in ANSI/VITA FMC form factor; (iii) 4-channel 16-bit 250 MS/s ADC board in ANSI/VITA FMC form factor. The experience of integrating the system prototype in a COTS MicroTCA.4 crate will be reported, as well as the planned developments.

Slides WECOCB07 [4.137 MB]

THPPC060

A PXI-Based Low Level Control for the Fast Pulsed Magnets in the CERN PS Complex

controls, kicker, timing, monitoring

1205

J. Schipper, E. Carlier, T. Fowler, T. Gharsa
CERN, Geneva, Switzerland

Fast pulsed magnet (kicker) systems are used for beam injection and extraction in the CERN PS complex. A novel approach, based on off-the-shelf PXI components, has been used for the consolidation of the low level part of their control system. Typical functionalities required like interlocking, equipment state control, thyratron drift stabilisation and protection, short circuit detection in magnets and transmission lines, pulsed signal acquisition and fine timing have been successfully integrated within a PXI controller. The controller comprises a National Instruments NI PXI-810x RT real time processor, a multifunctional RIO module including a Virtex-5 LX30 FPGA, a 1 GS/s digitiser and a digital delay module with 1 ns resolution. National Instruments LabVIEW development tools have been used to develop the embedded real time software as well as FPGA configuration and expert application programs. The integration within the CERN controls environment is performed using the Rapid Application Development Environment (RADE) software tools, developed at CERN.

Poster THPPC060 [0.887 MB]

THPPC067

New EPICS Drivers for Keck TCS Upgrade

EPICS, interface, controls, timing

1231

J.M. Johnson
W.M. Keck Observatory, Kamuela, USA

Keck Observatory is in the midst of a major telescope control system upgrade. This involves migrating from a VME based EPICS control system originally deployed on Motorola FRC40s VxWorks 5.1 and EPICS R3.13.0Beta12 to a distributed 64-bit X86 Linux servers running RHEL 2.6.33.x and EPICS R3.14.12.x. This upgrade brings a lot of new hardware to the project which includes Ethernet/IP connected PLCs, the ethernet connected DeltaTau Brick controllers, National Instruments MXI RIO, Heidenhain Encoders (and the Heidenhain ethernet connected Encoder Interface Box in particular), Symmetricom PCI based BC635 timing and synchronization cards, and serial line extenders and protocols. Keck has chosen to implement all new drivers using the ASYN framework. This paper will describe the various drivers used in the upgrade including those from the community and those developed by Keck which include BC635, MXI and Heidenhain EIB. It will also discuss the use of the BC635 as a local NTP reference clock and a service for the EPICS general time.

THPPC092

FAIR Timing System Developments Based on White Rabbit

timing, controls, network, interface

1288

C. Prados, R. Bär, D.H. Beck, J. Hoffmann, M. Kreider, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany
M. Kreider
Glyndŵr University, Wrexham, United Kingdom

A new timing system based on White Rabbit (WR) is being developed for the upcoming FAIR facility at GSI, in collaboration with CERN, other institutes and industry partners. The timing system is responsible for the synchronization of nodes with nanosecond accuracy and distribution of timing messages, which allows for real-time control of the accelerator equipment. WR is a fully deterministic Ethernet-based network for general data transfer and synchronization, which is based on Synchronous Ethernet and PTP. The ongoing development at GSI aims for a miniature timing system, which is part of a control system of a proton source, that will be used at one of the accelerators at FAIR. Such a timing system consists of a Data Master generating timing messages, which are forwarded by a WR switch to a handful of timing receiver. The next step is an enhancement of the robustness, reliability and scalability of the system. These features will be integrated in the forthcoming CRYRING control system in GSI. CRYRING serves as a prototype and testing ground for the final control system for FAIR. The contribution presents the overall design and status of the timing system development.

Poster THPPC092 [0.549 MB]

THPPC115

Fast Orbit Feedback Implementation at Alba Synchrotron

software, real-time, hardware, target

1328

X. Serra-Gallifa, S. Blanch-Torné, D. Fernández-Carreiras, A. Gutierrez-Milla, Z. Martí, O. Matilla, J. Moldes, A. Olmos, R. Petrocelli
CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain

After the successful accelerator commissioning and with the facility already in operation one of the top short term objectives pointed out by accelerator division was the Fast Orbit Feedback implementation (FOFB). The target of the FOFB system is to hold the electron beam position at submicron range both in vertical and horizontal planes correcting the inestabilities up to 120Hz. This increased beam stability performance is considered a major asset for the beamlines user operation. To achieve this target, the orbit position is acquired from the 88 Libera BPMs at a 10KHz sampling rate, distributed through an independent network and the corrections are calculated and sent to the 176 power supplies that drive the corrector coils. All this correction loop is executed at 10 KHz and the total latency of the system is characterized and minimized optimizing the bandwidth response.

Poster THPPC115 [0.732 MB]

THPPC125

Evaluation and Implementation of Advanced Process Control with the compactRIO Material of National Instrument

controls, LabView, feedback, real-time

1355

G. Maire, A. Kehrli, M. Pezzetti, S. Ravat
CERN, Geneva, Switzerland
B. Charnier, H. Coppier
ESIEE, Amiens, France

Programmable Logic Controller (PLC) is very commonly used in many industries and research applications for process control. However a very complex process control may require algorithms and performances beyond the capability of PLCs, very high-speed or precision controls may also require other solutions. This paper describes recent research conducted to implement advanced process controls with the cRIO material from National Instruments (decoupling of MIMO process control, steady state feedback, observer, Kalman filter, etc). The cRIO systems consist of an embedded real-time controller for communication and processing, a Reconfigurable Field Programmable Array (FPGA) and hot-swappable I/O modules. The paper presents experimental results and the ability of the cRIO to treat complex process control.

Poster THPPC125 [1.004 MB]

THPPC137

Time Domain Simulation Software of the APS Storage Ring Orbit Real-time Feedback System

feedback, simulation, software, storage-ring

1373

H. Shang, J. Carwardine, G. Decker, L. Emery, F. Lenkszus, N. Sereno, S. Xu
ANL, Argonne, USA

The APS storage ring real-time feedback (RTFB) system will be upgraded as part of the APS Upgrade project. The time domain simulation software is implemented to find the best parameters of correctors and evaluate the performance of different system configurations. The software includes two parts: the corrector noise model generator and the RTFB simulation. The corrector noise model generates the corrector noise data that are the input for the RTFB simulation. The corrector noise data are generated from the measured APS BPM turn-by-turn noise data, so that simulation actually reproduces the real machine. This paper introduces the algorithm and high-level software development of the corrector noise model generator and the RTFB simulation.
Work supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.

Poster THPPC137 [0.445 MB]

THCOCA02

White Rabbit Status and Prospects

network, distributed, controls, Ethernet

1445

J. Serrano, G. Daniluk, M.M. Lipiński, E. Van der Bij, T. Włostowski
CERN, Geneva, Switzerland
D.H. Beck, J. Hoffmann, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany

The White Rabbit (WR) project started off to provide a sequencing and synchronization solution for the needs of CERN and GSI. Since then, many other users have adopted it to solve problems in the domain of distributed hard real-time systems. The paper discusses the current performance of WR hardware, along with present and foreseen applications. It also describes current efforts to standardize WR under IEEE 1588 and recent developments on reliability of timely data distribution. Then it analyzes the role of companies and the commercial Open Hardware paradigm, finishing with an outline of future plans.

Slides THCOCA02 [7.955 MB]

FRCOBAB05

Distributed Feedback Loop Implementation in the RHIC Low Level RF Platform

cavity, LLRF, controls, damping

1501

F. Severino, M. Harvey, T. Hayes, G. Narayan, K.S. Smith
BNL, Upton, Long Island, New York, USA

Funding: Work supported by Brookhaven Science Associates, LLC under Contract No. DEAC02-98CH10886 with the U.S. Department of Energy.
We present a brief overview of distributed feedback systems based on the RHIC LLRF Platform. The general architecture and sub-system components of a complex feedback system are described, emphasizing the techniques and features employed to achieve deterministic and low latency data and timing delivery between local and remote sub-systems: processors, FPGA fabric components and the high level control system. In particular, we will describe how we make use of the platform to implement a widely distributed multi-processor and FPGA based longitudinal damping system, which relies on task sharing, tight synchronization and integration to achieve the desired functionality and performance.

Slides FRCOBAB05 [3.147 MB]