WEPMS —  Poster   (12-Oct-11   13:30—15:00)
Chair: J.M. Meyer, ESRF, Grenoble, France
Paper Title Page
WEPMS001 Interconnection Test Framework for the CMS Level-1 Trigger System 973
  • J. Hammer
    CERN, Geneva, Switzerland
  • M. Magrans de Abril
    UW-Madison/PD, Madison, Wisconsin, USA
  • C.-E. Wulz
    HEPHY, Wien, Austria
  The Level-1 Trigger Control and Monitoring System is a software package designed to configure, monitor and test the Level-1 Trigger System of the Compact Muon Solenoid (CMS) experiment at CERN's Large Hadron Collider. It is a large and distributed system that runs over 50 PCs and controls about 200 hardware units. The Interconnection Test Framework (ITF), a generic and highly flexible framework for creating and executing hardware tests within the Level-1 Trigger environment is presented. The framework is designed to automate testing of the 13 major subsystems interconnected with more than 1000 links. Features include a web interface to create and execute tests, modeling using finite state machines, dependency management, automatic configuration, and loops. Furthermore, the ITF will replace the existing heterogeneous testing procedures and help reducing maintenance and complexity of operation tasks. Finally, an example of operational use of the Interconnection Test Framework is presented. This case study proves the concept and describes the customization process and its performance characteristics.  
poster icon Poster WEPMS001 [0.576 MB]  
WEPMS003 A Testbed for Validating the LHC Controls System Core Before Deployment 977
  • J. Nguyen Xuan, V. Baggiolini
    CERN, Geneva, Switzerland
  Since the start-up of the LHC, it is crucial to carefully test core controls components before deploying them operationally. The Testbed of the CERN accelerator controls group was developed for this purpose. It contains different hardware (PPC, i386) running different operating systems (Linux and LynxOS) and core software components running on front-ends, communication middleware and client libraries. The Testbed first executes integration tests to verify that the components delivered by individual teams interoperate, and then system tests, which verify high-level, end-user functionality. It also verifies that different versions of components are compatible, which is vital, because not all parts of the operational LHC control system can be upgraded simultaneously. In addition, the Testbed can be used for performance and stress tests. Internally, the Testbed is driven by Bamboo, a Continuous Integration server, which builds and deploys automatically new software versions into the Testbed environment and executes the tests continuously to prevent from software regression. Whenever a test fails, an e-mail is sent to the appropriate persons. The Testbed is part of the official controls development process wherein new releases of the controls system have to be validated before being deployed operationally. Integration and system tests are an important complement to the unit tests previously executed in the teams. The Testbed has already caught several bugs that were not discovered by the unit tests of the individual components.
* http://cern.ch/jnguyenx/ControlsTestBed.html
poster icon Poster WEPMS003 [0.111 MB]  
WEPMS005 Automated Coverage Tester for the Oracle Archiver of WinCC OA 981
  • A. Voitier, P. Golonka, M. Gonzalez-Berges
    CERN, Geneva, Switzerland
  A large number of control systems at CERN are built with the commercial SCADA tool WinCC OA. They cover projects in the experiments, accelerators and infrastructure. An important component is the Oracle archiver used for long term storage of process data (events) and alarms. The archived data provide feedback to the operators and experts about how the system was behaving at particular moment in the past. In addition a subset of these data is used for offline physics analysis. The consistency of the archived data has to be ensured from writing to reading as well as throughout updates of the control systems. The complexity of the archiving subsystem comes from the multiplicity of data types, required performance and other factors such as operating system, environment variables or versions of the different software components, therefore an automatic tester has been implemented to systematically execute test scenarios under different conditions. The tests are based on scripts which are automatically generated from templates. Therefore they can cover a wide range of software contexts. The tester has been fully written in the same software environment as the targeted SCADA system. The current implementation is able to handle over 300 test cases, both for events and alarms. It has enabled to report issues to the provider of WinCC OA. The template mechanism allows sufficient flexibility to adapt the suite of tests to future needs. The developed tools are generic enough to be used to tests other parts of the control systems.  
poster icon Poster WEPMS005 [0.279 MB]  
WEPMS006 Automated testing of OPC Servers 985
  • B. Farnham
    CERN, Geneva, Switzerland
  CERN relies on OPC Server implementations from 3rd party device vendors to provide a software interface to their respective hardware. Each time a vendor releases a new OPC Server version it is regression tested internally to verify that existing functionality has not been inadvertently broken during the process of adding new features. In addition bugs and problems must be communicated to the vendors in a reliable and portable way. This presentation covers the automated test approach used at CERN to cover both cases: Scripts are written in a domain specific language specifically created for describing OPC tests and executed by a custom software engine driving the OPC Server implementation.  
poster icon Poster WEPMS006 [1.384 MB]  
WEPMS007 Backward Compatibility as a Key Measure for Smooth Upgrades to the LHC Control System 989
  • V. Baggiolini, M. Arruat, D. Csikos, R. Gorbonosov, P. Tarasenko, Z. Zaharieva
    CERN, Geneva, Switzerland
  Now that the LHC is operational, a big challenge is to upgrade the control system smoothly, with minimal downtime and interruptions. Backward compatibility (BC) is a key measure to achieve this: a subsystem with a stable API can be upgraded smoothly. As part of a broader Quality Assurance effort, the CERN Accelerator Controls group explored methods and tools supporting BC. We investigated two aspects in particular: (1) "Incoming dependencies", to know which part of an API is really used by clients and (2) BC validation, to check that a modification is really backward compatible. We used this approach for Java APIs and for FESA devices (which expose an API in the form of device/property sets). For Java APIs, we gather dependency information by regularly running byte-code analysis on all the 1000 Jar files that belong to the control system and find incoming dependencies (methods calls and inheritance). An Eclipse plug-in we developed shows these incoming dependencies to the developer. If an API method is used by many clients, it has to remain backward compatible. On the other hand, if a method is not used, it can be freely modified. To validate BC, we are exploring the official Eclipse tools (PDE-API tools), and others that check BC without need for invasive technology such as OSGi. For FESA devices, we instrumented key components of our controls system to know which devices and properties are in use. This information is collected in the Controls Database and is used (amongst others) by the FESA design tools in order to prevent the FESA class developer from breaking BC.  
WEPMS008 Software Tools for Electrical Quality Assurance in the LHC 993
  • M. Bednarek
    CERN, Geneva, Switzerland
  • J. Ludwin
    IFJ-PAN, Kraków, Poland
  There are over 1600 superconducting magnet circuits in the LHC machine. Many of them consist of a large number of components electrically connected in series. This enhances the sensitivity of the whole circuits to electrical faults of individual components. Furthermore, circuits are equipped with a large number of instrumentation wires, which are exposed to accidental damage or swapping. In order to ensure safe operation, an Electrical Quality Assurance (ELQA) campaign is needed after each thermal cycle. Due to the complexity of the circuits, as well as their distant geographical distribution (tunnel of 27km circumference divided in 8 sectors), suitable software and hardware platforms had to be developed. The software combines an Oracle database, LabView data acquisition applications and PHP-based web follow-up tools. This paper describes the software used for the ELQA of the LHC.  
poster icon Poster WEPMS008 [8.781 MB]  
MicroTCA.4: a New Hardware Standard for Accelerators and Experiments  
  • K. Rehlich
    DESY, Hamburg, Germany
  Several accelerator labs developed an extension for the MicroTCA standard together with industrial partners within the PICMG organization. This new MTCA.4 standard adds the required IO, clock and trigger capabilities to the telco dominated basic specifications. This paper describes the unique technology for high resolution and high performance front-end data acquisition and control. MTCA.4 provides comfortable sized Rear Transition Modules, high speed serial communication, precision clock distribution and full management. This make it an ideal choice for high precision analog IO in large installations. The European XFEL project is based on this new standard and several other labs are in a prototyping or evaluation phase.  
poster icon Poster WEPMS009 [3.689 MB]  
WEPMS011 The Timing Master for the FAIR Accelerator Facility 996
  • R. Bär, T. Fleck, M. Kreider, S. Mauro
    GSI, Darmstadt, Germany
  One central design feature of the FAIR accelerator complex is a high level of parallel beam operation, imposing ambitious demands on the timing and management of accelerator cycles. Several linear accelerators, synchrotrons, storage rings and beam lines have to be controlled and re-configured for each beam production chain on a pulse-to-pulse basis, with cycle lengths ranging from 20 ms to several hours. This implies initialization, synchronization of equipment on the time scale down to the ns level, interdependencies, multiple paths and contingency actions like emergency beam dump scenarios. The FAIR timing system will be based on White Rabbit [1] network technology, implementing a central Timing Master (TM) unit to orchestrate all machines. The TM is subdivided into separate functional blocks: the Clock Master, which deals with time and clock sources and their distribution over WR, the Management Master, which administrates all WR timing receivers, and the Data Master, which schedules and coordinates machine instructions and broadcasts them over the WR network. The TM triggers equipment actions based on the transmitted execution time. Since latencies in the low μs range are required, this paper investigates the possibilities of parallelisation in programmable hardware and discusses the benefits to either a distributed or monolithic timing master architecture. The proposed FPGA based TM will meet said timing requirements while providing fast reaction to interlocks and internal events and offers parallel processing of multiple signals and state machines.
[1] J. Serrano, et al, "The White Rabbit Project", ICALEPCS 2009.
Comparative Evaluation of IEEE-1588 Precision Time Protocol for the Synchronized Operation of Tokamak Device  
  • M.K. Park, S. Lee, T.G. Lee, W.R. Lee, S.W. Yun
    NFRI, Daejon, Republic of Korea
  Funding: The Korean Ministry of Education, Science and Technology
Recently the International Thermonuclear Experimental Reactor (ITER), which is the largest project in scale to construct a fusion reactor for the research of fusion energy source jointly with seven participants, has chosen IEEE-1588 precision time protocol (PTP) as a timing system standard for precisely synchronizing tokamak operation and plasma experiments. The IEEE-1588 PTP was designed as a standard for precision clock synchronization protocol for network measurements and control systems, and guarantees higher accuracy (less than sub-microsecond) than using NTP and more economical implementation than using GPS. Besides the original purpose, the uses are expanding to the provision of event timing and synchronization capabilities for large experimental facilities like ITER. On the other hands, many working tokamaks have operated with own timing systems having non-standard protocols. The Korea Superconducting Tokamak Advanced Research (KSTAR) has successfully operated the home-made timing system with the following features; PMC foam-factor with PCI/PCI-X interface, using EPICS 3.14.12 framework, board driver in VxWork5.5.1 and Linux2.6.x platforms, a master clock of 200MHz, timing accuracy less than 50ns, 8 output ports for trigger or clock signals, 8 configurable multi-triggering sections and provision of accurate time referenced to GPS time. This paper describes the result of evaluating IEEE-1588 PTP for tokamak and its detail implementation, and also the comparative analysis with KSTAR timing system after operating them in KSTAR during the 4th campaign in 2011.
poster icon Poster WEPMS012 [3.147 MB]  
WEPMS013 Timing System of the Taiwan Photon Source 999
  • C.Y. Wu, Y.-T. Chang, J. Chen, Y.-S. Cheng, P.C. Chiu, K.T. Hsu, K.H. Hu, C.H. Kuo, D. Lee, C.Y. Liao
    NSRRC, Hsinchu, Taiwan
  The timing system of the Taiwan Photon Source provides synchronization for electron gun, modulators of linac, pulse magnet power supplies, booster power supply ramp, bucket addressing of storage ring, diagnostic equipments, beamline gating signal for top-up injection. The system is based on an event distribution system that broadcasts the timing events over a optic fiber network, and decodes and processes them at the timing event receivers. The system supports uplink functionality which will be used for the fast interlock system to distribute signals like beam dump and post-mortem trigger with 10 μsec response time. The hardware of the event system is a new design that is based on 6U CompactPCI form factor. This paper describes the technical solution, the functionality of the system and some applications that are based on the timing system.  
WEPMS015 NSLS-II Booster Timing System 1003
  • P.B. Cheblakov, S.E. Karnaev
    BINP SB RAS, Novosibirsk, Russia
  • J.H. De Long
    BNL, Upton, Long Island, New York, USA
  The NSLS-II light source includes the main storage ring with beam lines and injection part consisting of 200 MeV linac, 3 GeV booster synchrotron and two transport lines. The booster timing system is a part of NSLS-II timing system which is based on Event Generator (EVG) and Event Receivers (EVRs) fromμResearch Finland. The booster timing is based on the external events coming from NSLS-II EVG: "Pre-Injection", "Injection", "Pre-Extraction", "Extraction". These events are referenced to the specified bunch of the Storage Ring and correspond to the first bunch of the booster. EVRs provide two scales for triggering both of the injection and the extraction pulse devices. The first scale provides triggering of the pulsed septums and the bump magnets in the range of milliseconds and uses TTL outputs of EVR, the second scale provides triggering of the kickers in the range of microseconds and uses CML outputs. EVRs also provide the timing of a booster cycle operation and events for cycle-to-cycle updates of pulsed and ramping parameters, and the booster beam instrumentation synchronization. This paper describes the final design of the booster timing system. The timing system functional and block diagrams are presented.  
poster icon Poster WEPMS015 [0.799 MB]  
WEPMS016 Network on Chip Master Control Board for Neutron's Acquisition 1006
  • E. Ruiz-Martinez, T. Mary, P. Mutti, J. Ratel, F. Rey
    ILL, Grenoble, France
  In the neutron scattering instruments at the Institute Laue-Langevin, one of the main challenges for the acquisition control is to generate the suitable signalling for the different modes of neutron acquisition. An inappropriate management could cause loss of information during the course of the experiments and in the subsequent data analysis. It is necessary to define a central element to provide synchronization to the rest of the units. The backbone of the proposed acquisition control system is the denominated master acquisition board. This main board is designed to gather together the modes of neutron acquisition used in the facility, and make it common for all the instruments in a simple, modular and open way, giving the possibility of adding new performances. The complete system also includes a display board and n histogramming modules connected to the neutrons detectors. The master board consists of a VME64X configurable high density I/O connection carrier board based on latest Xilinx Virtex-6T FPGA. The internal architecture of the FPGA is designed as a Network on Chip (NoC) approach. It represents a switch able to communicate efficiently the several resources available in the board (PCI Express, VME64x Master/Slave, DDR3 controllers and user's area). The core of the global signal synchronization is fully implemented in the FPGA, the board has a completely user configurable IO front-end to collect external signals, to process them and to distribute the synchronization control via the bus VME to the others modules involved in the acquisition.  
poster icon Poster WEPMS016 [7.974 MB]  
WEPMS017 The Global Trigger Processor: A VXS Switch Module for Triggering Large Scale Data Acquisition Systems 1010
  • S.R. Kaneta, C. Cuevas, H. Dong, W. Gu, E. Jastrzembski, N. Nganga, B.J. Raydo, J. Wilson
    JLAB, Newport News, Virginia, USA
  Funding: Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177.
The 12 GeV upgrade for Jefferson Lab's Continuous Electron Beam Accelerator Facility requires the development of a new data acquisition system to accommodate the proposed 200 kHz Level 1 trigger rates expected for fixed target experiments at 12 GeV. As part of a suite of trigger electronics comprised of VXS switch and payload modules, the Global Trigger Processor (GTP) will handle up to 32,768 channels of preprocessed trigger information data from the multiple detector systems that surround the beam target at a system clock rate of 250 MHz. The GTP is configured with user programmable Physics trigger equations and when trigger conditions are satisfied, the GTP will activate the storage of data for subsequent analysis. The GTP features an Altera Stratix IV GX FPGA allowing interface to 16 Sub-System Processor modules via 32 5-Gbps links, DDR2 and flash memory devices, two gigabit Ethernet interfaces using Nios II embedded processors, fiber optic transceivers, and trigger output signals. The GTP's high-bandwidth interconnect with the payload modules in the VXS crate, the Ethernet interface for parameter control, status monitoring, and remote update, and the inherent nature of its FPGA give it the flexibility to be used large variety of tasks and adapt to future needs. This paper details the responsibilities of the GTP, the hardware's role in meeting those requirements, and elements of the VXS architecture that facilitated the design of the trigger system. Also presented will be the current status of development including significant milestones and challenges.
poster icon Poster WEPMS017 [0.851 MB]  
WEPMS019 Measuring Angle with Pico Meter Resolution 1014
  • P. Mutti, M. Jentschel, T. Mary, F. Rey
    ILL, Grenoble, France
  • G. Mana, E. Massa
    INRIM, Turin, Italy
  The kilogram is the only remaining fundamental unit within the SI system that is defined in terms of a material artefact (a PtIr cylinder kept in Paris). Therefore, one of the major tasks of modern metrology is the redefinition of the kilogram on the basis of a natural quantity or of a fundamental constant. However, any kilogram redefinition must approach a 10-8 relative accuracy in its practical realization. A joint research project amongst the major metrology institutes in Europe has proposed the redefinition of the kilogram based on the mass of the 12C atom. The goal can be achieved by counting in a first step the number of atoms in a macroscopic weighable object and, in a second step, by weighing the atom by means of measuring its Compton frequency vC. It is in the second step of the procedure, where the ILL is playing a fundamental role with GAMS, the high-resolution γ-ray spectrometer. Energies of the γ-rays emitted in the decay of the capture state to the ground state of a daughter nucleus after a neutron capture reaction can be measured with high precision. In order to match the high demand in angle measurement accuracy, a new optical interferometer with 10 picorad resolution and linearity over a total measurement range of 15° and high stability of about 0.1 nrad/hour has been developed. To drive the interferometer, a new FPGA based electronics for the heterodyne frequency generation and for real time phase measurement and axis control has been realized. The basic concepts of the FPGA implementation will be revised.  
poster icon Poster WEPMS019 [6.051 MB]  
WEPMS020 NSLS-II Booster Power Supplies Control 1018
  • P.B. Cheblakov, S.E. Karnaev, S.S. Serednyakov
    BINP SB RAS, Novosibirsk, Russia
  • W. Louie, Y. Tian
    BNL, Upton, Long Island, New York, USA
  The NSLS-II booster Power Supplies (PSs) [1] are divided into two groups: ramping PSs providing passage of the beam during the beam ramp in the booster from 200 MeV up to 3 GeV at 300 ms time interval, and pulsed PSs providing beam injection from the linac and extraction to the Storage Ring. A special set of devices was developed at BNL for the NSLS-II magnetic system PSs control: Power Supply Controller (PSC) and Power Supply Interface (PSI). The PSI has one or two precision 18-bit DACs, nine channels of ADC for each DAC and digital input/outputs. It is capable of detecting the status change sequence of digital inputs with 10 ns resolution. The PSI is placed close to current regulators and is connected to the PSC via fiber-optic 50 Mbps data link. The PSC communicates with EPICS IOC through a 100 Mbps Ethernet port. The main function of IOC includes ramp curve upload, ADC waveform data download, and various process variable control. The 256 Mb DDR2 memory on PSC provides large storage for up to 16 ramping tables for the both DACs, and 20 second waveform recorder for all the ADC channels. The 100 Mbps Ethernet port enables real time display for 4 ADC waveforms. This paper describes a project of the NSLS-II booster PSs control. Characteristic features of the ramping magnets control and pulsed magnets control in a double-injection mode of operation are considered in the paper. First results of the control at PS testing stands are presented.
[1] Power Supply Control System of NSLS-II, Y. Tian, W. Louie, J. Ricciardelli, L.R. Dalesio, G. Ganetis, ICALEPCS2009, Japan
poster icon Poster WEPMS020 [1.818 MB]  
WEPMS022 The Controller Design for Kicker Magnet Adjustment Mechanism in SSRF 1021
  • R. Wang, R. Chen, Z.H. Chen, M. Gu
    SINAP, Shanghai, People's Republic of China
  The kicker magnet adjustment mechanism controller in SSRF is to improve the efficiency of injection by changing the magnet real-time, especially in the top-up mode. The controller mainly consists of Programmable Logic Controller (PLC), stepper motor, reducer, worm and mechanism. PLC controls the stepper motors for adjusting the azimuth of the magnet, monitors and regulates the magnet with inclinometer sensor. It also monitors the interlock. In addition, the controller is provided with local and remote working mode. This paper mainly introduces related hardware and software designs for this device.  
poster icon Poster WEPMS022 [0.173 MB]  
WEPMS023 ALBA Timing System - A Known Architecture with Fast Interlock System Upgrade 1024
  • O. Matilla, D.B. Beltrán, D.F.C. Fernández-Carreiras, J.J. Jamroz, J. Klora, J. Moldes, R. Suñé
    CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain
  Like most of the newest synchrotron facilities the ALBA Timing System works on event based architecture. Its main particularity is that integrated with the Timing system a Fast Interlock System has been implemented which allows for an automated and synchronous reaction time from any-to-any point of the machine faster than 5μs. The list of benefits of combining both systems is large: very high flexibility, reuse of the timing actuators, direct synchronous output in different points of the machine reacting to an interlock, implementation of the Fast Interlock with very low cost increase as the timing optic fiber network is reused or the possibility of combined diagnostic tools implementation for triggers and interlocks. To enhance this last point a global timestamp of 8ns accuracy that could be used both for triggers and interlocks has been implemented. The system has been designed, installed and extensively used during the Storage Ring commissioning with very good results.  
poster icon Poster WEPMS023 [0.920 MB]  
WEPMS024 ALBA High Voltage Splitter - Power Distribution to Ion Pumps 1028
  • J.J. Jamroz, E. Al-dmour, D.B. Beltrán, J. Klora, R. Martin, O. Matilla, S. Rubio-Manrique
    CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain
  High Voltage Splitter (HVS) is an equipment designed in Alba that allows a high voltage (HV) distribution (up to +7kV) from one ion pump controller up to eight ion pumps. Using it, the total number of high voltage power supplies needed in Alba's vacuum installation has decreased significantly. The current drawn by each splitter channel is measured independently inside a range from 10nA up to 10mA with 5% accuracy, those measurements are a base for vacuum pressure calculations. A relation, current-pressure depends mostly on the ion pump type, so different tools providing the full calibration flexibility have been implemented. Splitter settings, status and recorded data are accessible over a 10/100 Base-T Ethernet network, none the less a local (manual) control was implemented mostly for service purposes. The device supports also additional functions as a HV cable interlock, pressure interlock output cooperating with the facility's Equipment Protection System (EPS), programmable pressure warnings/alarms and automatic calibration process based on an external current source. This paper describes the project, functionality, implementation, installation and operation as a part of the vacuum system at Alba.  
poster icon Poster WEPMS024 [3.734 MB]  
WEPMS025 Low Current Measurements at ALBA 1032
  • J. Lidón-Simon, D.F.C. Fernández-Carreiras, J.V. Gigante, J.J. Jamroz, J. Klora, O. Matilla
    CELLS-ALBA Synchrotron, Cerdanyola del Vallès, Spain
  High accuracy low current readout is an extensively demanded technique in 3rd generation synchrotrons. Whether reading from scintillation excited large-area photodiodes for beam position measurement or out of gold meshes or metallic coated surfaces in drain-current based intensity monitors, low current measurement devices are an ubiquitous need both for diagnostics and data acquisition in today's photon labs. In order to tackle the problem of measuring from various sources of different nature and magnitude synchronously, while remaining flexible at the same time, ALBA has developed a 4 independent channel electrometer. It is based on transimpedance amplifiers and integrates high resolution ADC converters and an 10/100 Base-T Ethernet communication port. Each channel has independently configurable range, offset and low pass filter cut-off frequency settings and the main unit has external I/O to synchronize the data acquisition with the rest of the control system.  
poster icon Poster WEPMS025 [0.797 MB]  
WEPMS026 The TimBel Synchronization Board for Time Resolved Experiments at Synchrotron SOLEIL 1036
  • J.P. Ricaud, P. Betinelli-Deck, J. Bisou, X. Elattaoui, C. Laulhé, P. Monteiro, L.S. Nadolski, S. Ravy, G. Renaud, M.G. Silly, F. Sirotti
    SOLEIL, Gif-sur-Yvette, France
  Time resolved experiments are one of the major services that synchrotrons can provide to scientists. The short, high frequency and regular flashes of synchrotron light are a fantastic tool to study the evolution of phenomena over time. To carry out time resolved experiments, beamlines need to synchronize their devices with these flashes of light with a jitter shorter than the pulse duration. For that purpose, Synchrotron SOLEIL has developed the TimBeL board fully interfaced to TANGO framework. This paper presents the main features required by time resolved experiments and how we achieved our goals with the TimBeL board.  
poster icon Poster WEPMS026 [1.726 MB]  
WEPMS027 The RF Control System of the SSRF 150MeV Linac 1039
  • S.M. Hu, J.G. Ding, G.-Y. Jiang, L.R. Shen, M.H. Zhao, S.P. Zhong
    SINAP, Shanghai, People's Republic of China
  Shanghai Synchrotron Radiation Facility (SSRF) use a 150 MeV linear electron accelerator as injector, its RF system consists of many discrete devices. The control system is mainly composed of a VME controller and a home-made signal conditioner with DC power supplies. The uniform signal conditioner serves as a hardware interface between the controller and the RF components. The DC power supplies are used for driving the mechanical phase shifters. The control software is based on EPICS toolkit. Device drivers and related runtime database for the VME modules were developed. The operator interface was implemented by EDM.  
poster icon Poster WEPMS027 [0.702 MB]  
WEPMS028 Online Evaluation of New DBPM Processors at SINAP 1041
  • Y.B. Leng, G.Q. Huang, L.W. Lai, Y.B. Yan, X. Yi
    SSRF, Shanghai, People's Republic of China
  In this paper, we report our online evaluation results for new digital BPM signal processors, which are developed for the SSRF and the new Shanghai SXFEL facility. Two major prototypes have been evaluated. The first algorithm evaluation prototype is built using commercial development toolkits modules in order to test various digital processing blocks. The second prototype is designed and fabricated from chips level in order to evaluate the hardware performances of different functional modules and assembled processor.  
poster icon Poster WEPMS028 [0.546 MB]