WEPMN —  Poster   (12-Oct-11   13:30—15:00)
Chair: J.M. Meyer, ESRF, Grenoble, France

Paper	Title	Page
WEPMN001	Experience in Using Linux Based Embedded Controllers with EPICS Environment for the Beam Transport in SPES Off–Line Target Prototype	875
	M. Montis, M.G. Giacchini INFN/LNL, Legnaro (PD), Italy
	EPICS [1] was chosen as general framework to develop the control system of SPES facility under construction at LNL [2]. We report some experience in using some commercial devices based on Debian Linux to control the electrostatic deflectors installed on the beam line at the output of target chamber. We discuss this solution and compare it to other IOC implementations in use in the Target control system. [1] http://www.aps.anl.gov/epics/ [2] http://www.lnl.infn.it/~epics * M.Montis, MS thesis: http://www.lnl.infn.it/~epics/THESIS/TesiMaurizioMontis.pdf
	Poster WEPMN001 [1.036 MB]
WEPMN005	Spiral2 Control Command: a Standardized Interface between High Level Applications and EPICS IOCs	879
	C.H. Haquin, P. Gillette, E. Lemaître, L. Philippe, D.T. Touchard GANIL, Caen, France F. Gougnaud, Y. Lussignol CEA/DSM/IRFU, France
	The SPIRAL2 linear accelerator will produce entirely new particle beams enabling exploration of the boundaries of matter. Coupled with the existing GANIL machine this new facility will produce light and heavy exotic nuclei at extremely high intensities. The field deployment of the Control System relies on Linux PCs and servers, VME VxWorks crates and Siemens PLCs; equipment will be addressed either directly or using a Modbus/TCP field bus network. Several laboratories are involved in the software development of the control system. In order to improve efficiency of the collaboration, special care is taken of the software organization. During the development phase, in a context of tough budget and time constraints, this really makes sense, but also for the exploitation of the new machine, it helps us to design a control system that will require as little effort as possible for maintenance and evolution. The major concepts of this organization are the choice of EPICS, the definition of an EPICS directory tree specific to SPIRAL2, called "topSP2": this is our reference work area for development, integration and exploitation, and the use of version control system (SVN) to store and share our developments independently of the multi-site dimension of the project. The next concept is the definition of a "standardized interface" between high level applications programmed in Java and EPICS databases running in IOCs. This paper relates the rationale and objectives of this interface and also its development cycle from specification using UML diagrams to testing on the actual equipment.
	Poster WEPMN005 [0.945 MB]
WEPMN006	Commercial FPGA Based Multipurpose Controller: Implementation Perspective	882
	I. Arredondo, D. Belver, P. Echevarria, M. Eguiraun, H. Hassanzadegan, M. del Campo ESS-Bilbao, Zamudio, Spain V. Etxebarria, J. Jugo University of the Basque Country, Faculty of Science and Technology, Bilbao, Spain N. Garmendia, L. Muguira ESS Bilbao, Bilbao, Spain
	Funding: The present work is supported by the Basque Government and Spanish Ministry of Science and Innovation. This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,…), methods to create and use the EPICS server (put, get, monitor,…), mathematical methods to process the data (numeric format conversions,…) and methods to create/initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. It is the developed main class which is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao facility.
	Poster WEPMN006 [0.559 MB]
WEPMN008	Function Generation and Regulation Libraries and their Application to the Control of the New Main Power Converter (POPS) at the CERN CPS	886
	Q. King, S.T. Page, H. Thiesen CERN, Geneva, Switzerland M. Veenstra EBG MedAustron, Wr. Neustadt, Austria
	Power converter control for the LHC is based on an embedded control computer called a Function Generator/Controller (FGC). Every converter includes an FGC with responsibility for the generation of the reference current as a function of time and the regulation of the circuit current, as well as control of the converter state. With many new converter controls software classes in development it was decided to generalise several key components of the FGC software in the form of C libraries: function generation in libfg, regulation, limits and simulation in libreg and DCCT, ADC and DAC calibration in libcal. These libraries were first used in the software class dedicated to controlling the new 60MW main power converter (POPS) at the CERN CPS where regulation of both magnetic field and circuit current is supported. This paper reports on the functionality provided by each library and in particular libfg and libreg. The libraries are already being used by software classes in development for the next generation FGC for Linac4 converters, as well as the CERN SPS converter controls (MUGEF) and MedAustron converter regulation board (CRB).
	Poster WEPMN008 [3.304 MB]
WEPMN009	Simplified Instrument/Application Development and System Integration Using Libera Base Software Framework	890
	M. Kenda, T. Beltram, T. Juretič, B. Repič, D. Škvarč, Č. Valentinčič I-Tech, Solkan, Slovenia
	Development of many appliances used in scientific environment forces us to face similar challenges, often executed repeatedly. One has to design or integrate hardware components. Support for network and other communications standards needs to be established. Data and signals are processed and dispatched. Interfaces are required to monitor and control the behaviour of the appliances. At Instrumentation Technologies we identified and addressed these issues by creating a generic framework which is composed of several reusable building blocks. They simplify some of the tedious tasks and leave more time to concentrate on real issues of the application. Further more, the end product quality benefits from larger common base of this middle-ware. We will present the benefits on concrete example of instrument implemented on MTCA platform accessible over graphical user interface.
	Poster WEPMN009 [5.755 MB]
WEPMN011	Controlling the EXCALIBUR Detector	894
	J.A. Thompson, I. Horswell, J. Marchal, U.K. Pedersen Diamond, Oxfordshire, United Kingdom S.R. Burge, J.D. Lipp, T.C. Nicholls STFC/RAL, Chilton, Didcot, Oxon, United Kingdom
	EXCALIBUR is an advanced photon counting detector being designed and built by a collaboration of Diamond Light Source and the Science and Technology Facilities Council. It is based around 48 CERN Medipix III silicon detectors arranged as an 8x6 array. The main problem addressed by the design of the hardware and software is the uninterrupted collection and safe storage of image data at rates up to one hundred (2048x1536) frames per second. This is achieved by splitting the image into six 'stripes' and providing parallel data paths for them all the way from the detectors to the storage. This architecture requires the software to control the configuration of the stripes in a consistent manner and to keep track of the data so that the stripes can be subsequently stitched together into frames.
	Poster WEPMN011 [0.289 MB]
WEPMN012	PC/104 Asyn Drivers at Jefferson Lab	898
	J. Yan, T.L. Allison, S.D. Witherspoon JLAB, Newport News, Virginia, USA
	Funding: Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177. PC/104 embedded IOCs that run RTEMS and EPICS have been applied in many new projects at Jefferson Lab. Different commercial PC/104 I/O modules on the market such as digital I/O, data acquisition, and communication modules are integrated in our control system. AsynDriver, which is a general facility for interfacing device specific code to low level drivers, was applied for PC/104 serial communication I/O cards. We choose the ines GPIB-PC/104-XL as the GPIB interface module and developed the low lever device driver that is compatible with the asynDriver. The ines GPIB-PC/104-XL has iGPIB 72110 chip, which is register compatible with NEC uPD7210 in GPIB Talker/Listener applications. Instrument device support was created to provide access to the operating parameters of GPIB devices. Low level device driver for the serial communication board Model 104-COM-8SM was also developed to run under asynDriver. This serial interface board contains eight independent ports and provides effective RS-485, RS-422 and RS-232 multipoint communication. StreamDevice protocols were applied for the serial communications. The asynDriver in PC/104 IOC application provides standard interface between the high level device support and hardwire level device drivers. This makes it easy to develop the GPIB and serial communication applications in PC/104 IOCs.
WEPMN013	Recent Developments in Synchronised Motion Control at Diamond Light Source	901
	B.J. Nutter, T.M. Cobb, M.R. Pearson, N.P. Rees, F. Yuan Diamond, Oxfordshire, United Kingdom
	At Diamond Light Source the EPICS control system is used with a variety of motion controllers. The use of EPICS ensures a common interface over a range of motorised applications. We have developed a system to enable the use of the same interface for synchronised motion over multiple axes using the Delta Tau PMAC controller. Details of this work will be presented, along with examples and possible future developments.
WEPMN014	The Software and Hardware Architectural Design of the Vessel Thermal Map Real-Time System in JET	905
	D. Alves, A. Neto, D.F. Valcárcel IPFN, Lisbon, Portugal G. Arnoux, P. Card, S. Devaux, R.C. Felton, A. Goodyear, D. Kinna, P.J. Lomas, P. McCullen, A.V. Stephen, K-D. Zastrow CCFE, Abingdon, Oxon, United Kingdom S. Jachmich RMA, Brussels, Belgium
	The installation of ITER-relevant materials for the plasma facing components (PFCs) in the Joint European Torus (JET) is expected to have a strong impact on the operation and protection of the experiment. In particular, the use of all-beryllium tiles, which deteriorate at a substantially lower temperature than the formerly installed CFC tiles, imposes strict thermal restrictions on the PFCs during operation. Prompt and precise responses are therefore required whenever anomalous temperatures are detected. The new Vessel Thermal Map (VTM) real-time application collects the temperature measurements provided by dedicated pyrometers and Infra-Red (IR) cameras, groups them according to spatial location and probable offending heat source and raises alarms that will trigger appropriate protective responses. In the context of JET's global scheme for the protection of the new wall, the system is required to run on a 10 millisecond cycle communicating with other systems through the Real-Time Data Network (RTDN). In order to meet these requirements a Commercial Off-The-Shelf (COTS) solution has been adopted based on standard x86 multi-core technology, Linux and the Multi-threaded Application Real-Time executor (MARTe) software framework. This paper presents an overview of the system with particular technical focus on the configuration of its real-time capability and the benefits of the modular development approach and advanced tools provided by the MARTe framework. See the Appendix of F. Romanelli et al., Proceedings of the 23rd IAEA Fusion Energy Conference 2010, Daejeon, Korea
	Poster WEPMN014 [5.306 MB]
WEPMN015	Timing-system Solution for MedAustron; Real-time Event and Data Distribution Network	909
	R. Štefanič, J. Dedič, R. Tavčar Cosylab, Ljubljana, Slovenia J. Gutleber CERN, Geneva, Switzerland R. Moser EBG MedAustron, Wr. Neustadt, Austria
	MedAustron is an ion beam cancer therapy and research centre currently under construction in Wiener Neustadt, Austria. This facility features a synchrotron particle accelerator for light ions. A timing system is being developed for that class of accelerators targeted at clinical use as a product of close collaboration between MedAustron and Cosylab. We redesignedμResearch Finland transport layer's FPGA firmware, extending its capabilities to address specific requirements of the machine to come to a generic real-time broadcast network for coordinating actions of a compact, pulse-to-pulse modulation based particle accelerator. One such requirement is the need to support for configurable responses to timing events on the receiver side. The system comes with National Instruments LabView based software support, ready to be integrated into the PXI based front-end controllers. This paper explains the design process from initial requirements refinement to technology choice, architectural design and implementation. It elaborates the main characteristics of the accelerator that the timing system has to address, such as support for concurrently operating partitions, real-time and non real-time data transport needs and flexible configuration schemes for real-time response to timing event reception. Finally, the architectural overview is given, with the main components explained in due detail.
	Poster WEPMN015 [0.800 MB]
WEPMN016	Synchronously Driven Power Converter Controller Solution for MedAustron	912
	L. Šepetavc, J. Dedič, R. Tavčar Cosylab, Ljubljana, Slovenia J. Gutleber CERN, Geneva, Switzerland R. Moser EBG MedAustron, Wr. Neustadt, Austria
	MedAustron is an ion beam cancer therapy and research centre currently under construction in Wiener Neustadt, Austria. This facility features a synchrotron particle accelerator for light ions. Cosylab is closely working together with MedAustron on the development of a power converter controller (PCC) for the 260 deployed converters. The majority are voltage sources that are regulated in real-time via digital signal processor (DSP) boards. The in-house developed PCC operates the DSP boards remotely, via real-time fiber optic links. A single PCC will control up to 30 power converters that deliver power to magnets used for focusing and steering particle beams. Outputs of all PCCs must be synchronized within a time frame of at most 1 microsecond, which is achieved by integration with the timing system. This pulse-to-pulse modulation machine requires different waveforms for each beam generation cycle. Dead times between cycles must be kept low, therefore the PCC is reconfigured during beam generation. The system is based on a PXI platform from National Instruments running LabVIEW Real-Time. An in-house developed generic real-time optical link connects the PCCs to custom developed front-end devices. These FPGA-based hardware components facilitate integration with different types of power converters. All PCCs are integrated within the SIMATIC WinCC OA SCADA system which coordinates and supervises their operation. This paper describes the overall system architecture, its main components, challenges we faced and the technical solutions.
	Poster WEPMN016 [0.695 MB]
WEPMN017	PCI Hardware Support in LIA-2 Control System	916
	D. Bolkhovityanov, P.B. Cheblakov BINP SB RAS, Novosibirsk, Russia
	LIA-2 control system* is built on cPCI crates with x86-compatible processor boards running Linux. Slow electronics is connected via CAN-bus, while fast electronics (4MHz and 200MHz fast ADCs and 200MHz timers) are implemented as cPCI/PMC modules. Several ways to drive PCI control electronics in Linux were examined. Finally a userspace drivers approach was chosen. These drivers communicate with hardware via a small kernel module, which provides access to PCI BARs and to interrupt handling. This module was named USPCI (User-Space PCI access). This approach dramatically simplifies creation of drivers, as opposed to kernel drivers, and provides high reliability (because only a tiny and thoroughly-debugged piece of code runs in kernel). LIA-2 accelerator was successfully commissioned, and the solution chosen has proven adequate and very easy to use. Besides, USPCI turned out to be a handy tool for examination and debugging of PCI devices direct from command-line. In this paper available approaches to work with PCI control hardware in Linux are considered, and USPCI architecture is described. * "LIA-2 Linear Induction Accelerator Control System", this conference
	Poster WEPMN017 [0.954 MB]
WEPMN018	Performance Tests of the Standard FAIR Equipment Controller Prototype	919
	S. Rauch, R. Bär, W. Panschow, M. Thieme GSI, Darmstadt, Germany
	For the control system of the new FAIR accelerator facility a standard equipment controller, the Scalable Control Unit (SCU), is presently under development. First prototypes have already been tested in real applications. The controller combines an x86 ComExpress Board and an Altera Arria II FPGA. Over a parallel bus interface called the SCU bus, up to 12 slave boards can be controlled. Communication between CPU and FPGA is done by a PCIe link. We discuss the real time behaviour between the Linux OS and the FPGA Hardware. For the test, a Front-End Software Architecture (FESA) class, running under Linux, communicates with the PCIe bridge in the FPGA. Although we are using PCIe only for single 32 bit wide accesses to the FPGA address space, the performance still seems sufficient. The tests showed an average response time to IRQs of 50 microseconds with a 1.6 GHz Intel Atom CPU. This includes the context change to the FESA userspace application and the reply back to the FPGA. Further topics are the bandwidth of the PCIe link for single/burst transfers and the performance of the SCU bus communication.
WEPMN020	New Developments on Tore Supra Data Acquisition Units	922
	F. Leroux, G. Caulier, L. Ducobu, M. Goniche Association EURATOM-CEA, St Paul Lez Durance, France G. Antar American University of Beirut, Beirut, Lebanon
	Tore Supra data acquisition system (DAS) was designed in the early 1980s and has considerably evolved since then. Three generations of data acquisition units still coexist: Multibus, VME, and PCI bus system. The second generation, VME bus system, running LynxOS real-time operating system (OS) is diskless. The third generation, PCI bus system, allows to perform extensive data acquisition for infrared and visible video cameras that produce large amounts of data to handle. Nevertheless, this third generation was up to now provided with an hard drive and a non real-time operating system Microsoft Windows. Diskless system is a better solution for reliability and maintainability as they share common resources like kernel and file system. Moreover, open source real-time OS is now available which provide free and convenient solutions for DAS. As a result, it was decided to explore an alternative solution based on an open source OS with a diskless system for the fourth generation. In 2010, Linux distributions for VME bus and PCI bus systems have been evaluated and compared to LynxOS. Currently, Linux OS is fairly mature to be used on DAS with pre-emptive and real time features on Motorola PowerPC, x86 and x86 multi-core architecture. The results allowed to choose a Linux version for VME and PC platform for DAS on Tore Supra. In 2011, the Tore Supra DAS dedicated software was ported on a Linux diskless PCI platform. The new generation was successfully tested during real plasma experiment on one diagnostic. The new diagnostics for Tore Supra will be developed with this new set up.
	Poster WEPMN020 [0.399 MB]
WEPMN022	LIA-2 Power Supply Control System	926
	A. Panov, P.A. Bak, D. Bolkhovityanov BINP SB RAS, Novosibirsk, Russia
	LIA-2 is an electron Linear Induction Accelerator designed and built by BINP for flash radiography. Inductors get power from 48 modulators, grouped by 6 in 8 racks. Each modulator includes 3 control devices, connected via internal CAN bus to an embedded modulator controller, which runs Keil RTX real-time OS. Each rack includes a cPCI crate equipped with x86-compatible processor board running Linux*. Modulator controllers are connected to cPCI crate via external CAN bus. Additionally, brief modulator status is displayed on front indicator. Integration of control electronics into devices with high level of electromagnetic interferences is discussed, use of real-time OSes in such devices and interaction between them is described. *"LIA-2 Linear Induction Accelerator Control System", this conference
	Poster WEPMN022 [5.035 MB]
WEPMN023	The ATLAS Tile Calorimeter Detector Control System	929
	G. Ribeiro LIP, Lisboa, Portugal G. Arabidze MSU, East Lansing, Michigan, USA P. Lafarguette Université Blaise Pascal, Clermont-Ferrand, France S. Nemecek Czech Republic Academy of Sciences, Institute of Physics, Prague, Czech Republic
	The main task of the ATLAS Tile calorimeter Detector Control System (DCS) is to enable the coherent and safe operation of the calorimeter. All actions initiated by the operator, as well as all errors, warnings and alarms concerning the hardware of the detector are handled by DCS. The Tile calorimeter DCS controls and monitors mainly the low voltage and high voltage power supply systems, but it is also interfaced with the infrastructure (cooling system and racks), the calibration systems, the data acquisition system, configuration and conditions databases and the detector safety system. The system has been operational since the beginning of LHC operation and has been extensively used in the operation of the detector. In the last months effort was directed to the implementation of automatic recovery of power supplies after trips. Current status, results and latest developments will be presented.
	Poster WEPMN023 [0.404 MB]
WEPMN024	NSLS-II Beam Position Monitor Embedded Processor and Control System	932
	K. Ha, L.R. Dalesio, J.H. De Long, J. Mead, Y. Tian, K. Vetter BNL, Upton, New York, USA
	Funding: Work supported by DOE contract No: DE-AC02-98CH10886 NSLS-II is a 3 Gev 3rd generation light source that is currently under construction. A sub-micron Digital Beam Position Monitor (DBPM) system which is hardware electronics and embedded software processor and EPICS IOC has been successfully developed and tested in the ALS storage ring and BNL Lab.
WEPMN025	A New Fast Triggerless Acquisition System For Large Detector Arrays	935
	P. Mutti, M. Jentschel, J. Ratel, F. Rey, E. Ruiz-Martinez, W. Urban ILL, Grenoble, France
	Presently a common characteristic trend in low and medium energy nuclear physics is to develop more complex detector systems to form multi-detector arrays. The main objective of such an elaborated set-up is to obtain comprehensive information about the products of all reactions. State-of-art γ-ray spectroscopy requires nowadays the use of large arrays of HPGe detectors often coupled with anti-Compton active shielding to reduce the ambient background. In view of this complexity, the front-end electronics must provide precise information about energy, time and possibly pulse shape. The large multiplicity of the detection system requires the capability to process the multitude of signals from many detectors, fast processing and very high throughput of more that 106 data words/sec. The possibility to handle such a complex system using traditional analogue electronics has shown rapidly its limitation due, first of all, to the non negligible cost per channel and, moreover, to the signal degradation associated to complex analogue path. Nowadays, digital pulse processing systems are available, with performances, in terms of timing and energy resolution, equal when not better than the corresponding analogue ones for a fraction of the cost per channel. The presented system uses a combination of a 15-bit 100 MS/s digitizer with a PowerPC-based VME single board computer. Real-time processing algorithms have been developed to handle total event rates of more than 1 MHz, providing on-line display for single and coincidence events.
	Poster WEPMN025 [15.172 MB]
WEPMN026	Evolution of the CERN Power Converter Function Generator/Controller for Operation in Fast Cycling Accelerators	939
	D.O. Calcoen, Q. King, P.F. Semanaz CERN, Geneva, Switzerland
	Power converters in the LHC are controlled by the second generation of an embedded computer known as a Function Generator/Controller (FGC2). Following the success of this control system, new power converter installations at CERN will be based around an evolution of the design - a third generation called FGC3. The FGC3 will initially be used in the PS Booster and Linac4. This paper compares the hardware of the two generations of FGC and details the decisions made during the design of the FGC3.
	Poster WEPMN026 [0.586 MB]
WEPMN027	Fast Scalar Data Buffering Interface in Linux 2.6 Kernel	943
	A. Homs ESRF, Grenoble, France
	Key instrumentation devices like counter/timers, analog-to-digital converter and encoders provide scalar data input. Many of them allow fast acquisitions, but do not provide hardware triggering or buffering mechanisms. A Linux 2.4 kernel driver called Hook was developed at the ESRF as a generic software-triggered buffering interface. This work presents the portage of the ESRF Hook interface to the Linux 2.6 kernel. The interface distinguishes two independent functional groups: trigger event generators and data channels. Devices in the first group create software events, like hardware interrupts generated by timers or external signals. On each event, one or more device channels on the second group are read and stored in kernel buffers. The event generators and data channels to be read are fully configurable before each sequence. Designed for fast acquisitions, the Hook implementation is well adapted to multi-CPU systems, where the interrupt latency is notably reduced. On heavily loaded dual-core PCs running standard (non real time) Linux, data can be taken at 1 KHz without losing events. Additional features include full integration into the sysfs (/sys) virtual filesystem and hotplug devices support.
WEPMN028	Development of Image Data Acquisition System for 2D Detector at SACLA (SPring-8 XFEL)	947
	A. Kiyomichi, A. Amselem, T. Hirono, T. Ohata, R. Tanaka, M. Yamaga JASRI/SPring-8, Hyogo-ken, Japan T. Hatsui RIKEN/SPring-8, Hyogo, Japan
	The x-ray free electron laser facility SACLA (SPring-8 Angstrom Compact free electron LAser) was constructed and started beam commissioning from March 2011. For the requirements of proposed experiments at SACLA, x-ray multi-readout ports CCD detectors (MPCCD) have been developed to realize a system with the total amount of 4 Mega-pixels area and 16bit wide dynamic range at a frame rate of 60Hz shot rate. We have developed the image data-handling scheme using the event-synchronized data-acquisition system. The front-end system used the CameraLink interface that excels in abilities of real-time triggering and high-speed data transfer. For the total data rate up to 4Gbps, the image data are collected by dividing the CCD detector into eight segments, which handles 0.5M pixels each, and then sent to high-speed data storage in parallel. We prepared two types of Cameralink imaging system for the VME and PC base. The Image Distribution board is made up of logic-reconfigurable VME board with CameraLink mezzanine card. The front-end system of MPCCD detector consists of eight sets of Image Distribution boards. We plan to introduce the online lossless compression using FPGA with arithmetic coding algorithm. For wide adaptability of user requirements, we also prepared the PC based imaging system, which consists of Linux server and commercial CameraLink PCI interface. It does not contain compression function, but supports various type of CCD camera, for example, high-definition (1920x1080) single CCD camera.
	Poster WEPMN028 [5.574 MB]
WEPMN030	Power Supply Control Interface for the Taiwan Photon Source	950
	C.Y. Wu, J. Chen, Y.-S. Cheng, P.C. Chiu, K.T. Hsu, K.H. Hu, C.H. Kuo, D. Lee, C.Y. Liao, K.-B. Liu NSRRC, Hsinchu, Taiwan
	The Taiwan Photon Source (TPS) is a latest generation synchrotron light source. Stringent power supply specifications should be met to achieve design goals of the TPS. High precision power supply equipped with 20, 18, and 16 bits DAC for the storage ring dipole, quadrupole, and sextupole are equipped with Ethernet interfaces. Control interface include basic functionality and some advanced features which are useful for performance monitoring and post-mortem diagnostics. Power supply of these categories can be accessed by EPICS IOCs. The corrector power supplies' control interface is a specially designed embedded interface module which will be mounted on the corrector power supply cages to achieve required performance. The setting reference of the corrector power supply is generated by 20 bits DAC and readback is done by 24 bits ADC. The interface module has embedded EPICS IOC for slow control. Fast setting ports are also supported by the internal FPGA for orbit feedback supports.
WEPMN032	Development of Pattern Awareness Unit (PAU) for the LCLS Beam Based Fast Feedback System	954
	K.H. Kim, S. Allison, D. Fairley, T.M. Himel, P. Krejcik, D. Rogind, E. Williams SLAC, Menlo Park, California, USA
	LCLS is now successfully operating at its design beam repetition rate of 120 Hz, but in order to ensure stable beam operation at this high rate we have developed a new timing pattern aware EPICS controller for beam line actuators. Actuators that are capable of responding at 120 Hz are controlled by the new Pattern Aware Unit (PAU) as part of the beam-based feedback system. The beam at the LCLS is synchronized to the 60 Hz AC power line phase and is subject to electrical noise which differs according to which of the six possible AC phases is chosen from the 3-phase site power line. Beam operation at 120 Hz interleaves two of these 60 Hz phases and the feedback must be able to apply independent corrections to the beam pulse according to which of the 60 Hz timing patterns the pulse is synchronized to. The PAU works together with the LCLS Event Timing system which broadcasts a timing pattern that uniquely identifies each pulse when it is measured and allows the feedback correction to be applied to subsequent pulses belonging to the same timing pattern, or time slot, as it is referred to at SLAC. At 120 Hz operation this effectively provides us with two independent, but interleaved feedback loops. Other beam programs at the SLAC facility such as LCLS-II and FACET will be pulsed on other time slots and the PAUs in those systems will respond to their appropriate timing patterns. This paper describes the details of the PAU development: real-time requirements and achievement, scalability, and consistency. The operational results will also be described.
	Poster WEPMN032 [0.430 MB]
WEPMN034	YAMS: a Stepper Motor Controller for the FERMI@Elettra Free Electron Laser	958
	A. Abrami, M. De Marco, M. Lonza, D. Vittor ELETTRA, Basovizza, Italy
	Funding: The work was supported in part by the Italian Ministry of University and Research under grants FIRB-RBAP045JF2 and FIRB-RBAP06AWK3 New projects, like FERMI@Elettra, demand for standardization of the systems in order to cut development and maintenance costs. The various motion control applications foreseen in this project required a specific controller able to flexibly adapt to any need while maintaining a common interface to the control system to minimize software development efforts. These reasons led us to design and build "Yet Another Motor Subrack", YAMS, a 3U chassis containing a commercial stepper motor controller, up to eight motor drivers and all the necessary auxiliary systems. The motors can be controlled locally by means of an operator panel or remotely through an Ethernet interface and a dedicated Tango device server. The paper describes the details of the project and the deployment issues.
	Poster WEPMN034 [4.274 MB]
WEPMN036	Comparative Analysis of EPICS IOC and MARTe for the Development of a Hard Real-Time Control Application	961
	A. Barbalace, A. Luchetta, G. Manduchi, C. Taliercio Consorzio RFX, Associazione Euratom-ENEA sulla Fusione, Padova, Italy B. Carvalho, D.F. Valcárcel IPFN, Lisbon, Portugal
	EPICS is used worldwide to build distributed control systems for scientific experiments. The EPICS software suite is based around the Channel Access (CA) network protocol that allows the communication of different EPICS clients and servers in a distributed architecture. Servers are called Input/Output Controllers (IOCs) and perform real-world I/O or local control tasks. EPICS IOCs were originally designed for VxWorks to meet the demanding real-time requirements of control algorithms and have lately been ported to different operating systems. The MARTe framework has recently been adopted to develop an increasing number of hard real-time systems in different fusion experiments. MARTe is a software library that allows the rapid and modular development of stand-alone hard real-time control applications on different operating systems. MARTe has been created to be portable and during the last years it has evolved to follow the multicore evolution. In this paper we review several implementation differences between EPICS IOC and MARTe. We dissect their internal data structures and synchronization mechanisms to understand what happens behind the scenes. Differences in the component based approach and in the concurrent model of computation in EPICS IOC and MARTe are explained. Such differences lead to distinct time models in the computational blocks and distinct real-time capabilities of the two frameworks that a developer must be aware of.
	Poster WEPMN036 [2.406 MB]
WEPMN037	DEBROS: Design and Use of a Linux-like RTOS on an Inexpensive 8-bit Single Board Computer	965
	M.A. Davis NSCL, East Lansing, Michigan, USA
	As the power, complexity, and capabilities of embedded processors continues to grow, it is easy to forget just how much can be done with inexpensive single board computers based on 8-bit processors. When the proprietary, non-standard tools from the vendor for one such embedded computer became a major roadblock, I embarked on a project to expand my own knowledge and provide a more flexible, standards based alternative. Inspired by operating systems such as Unix, Linux, and Minix, I wrote DEBROS (the Davis Embedded Baby Real-time Operating System) [1], which is a fully pre-emptive, priority-based OS with soft real-time capabilities that provides a subset of standard Linux/Unix compatible system calls such as stdio, BSD sockets, pipes, semaphores, etc. The end result was a much more flexible, standards-based development environment which allowed me to simplify my programming model, expand diagnostic capabilities, and reduce the time spent monitoring and applying updates to the hundreds of devices in the lab currently using this hardware.[2] [1] http://groups.nscl.msu.edu/controls/files/DEBROS_User_Developer_Manual.doc [2] http://groups.nscl.msu.edu/controls/
	Poster WEPMN037 [0.112 MB]
WEPMN038	A Combined On-line Acoustic Flowmeter and Fluorocarbon Coolant Mixture Analyzer for the ATLAS Silicon Tracker	969
	A. Bitadze, R.L. Bates University of Glasgow, Glasgow, United Kingdom M. Battistin, S. Berry, P. Bonneau, J. Botelho-Direito, B. Di Girolamo, J. Godlewski, E. Perez-Rodriguez, L. Zwalinski CERN, Geneva, Switzerland N. Bousson, G.D. Hallewell, M. Mathieu, A. Rozanov CNRS/CPT, Marseille, France R. Boyd University of Oklahoma, Norman, Oklahoma, USA M. Doubek, V. Vacek, M. Vitek Czech Technical University in Prague, Faculty of Mechanical Engineering, Prague, Czech Republic K. Egorov Indiana University, Bloomington, Indiana, USA S. Katunin PNPI, Gatchina, Leningrad District, Russia S. McMahon STFC/RAL/ASTeC, Chilton, Didcot, Oxon, United Kingdom K. Nagai University of Tsukuba, Graduate School of Pure and Applied Sciences,, Tsukuba, Ibaraki, Japan
	An upgrade to the ATLAS silicon tracker cooling control system requires a change from C3F8 (molecular weight 188) coolant to a blend with 10-30% C2F6 (mw 138) to reduce the evaporation temperature and better protect the silicon from cumulative radiation damage at LHC. Central to this upgrade an acoustic instrument for measurement of C3F8/C2F6 mixture and flow has been developed. Sound velocity in a binary gas mixture at known temperature and pressure depends on the component concentrations. 50 kHz sound bursts are simultaneously sent via ultrasonic transceivers parallel and anti-parallel to the gas flow. A 20 MHz transit clock is started synchronous with burst transmission and stopped by over-threshold received sound pulses. Transit times in both directions, together with temperature and pressure, enter a FIFO memory 100 times/second. Gas mixture is continuously analyzed using PVSS-II, by comparison of average sound velocity in both directions with stored velocity-mixture look-up tables. Flow is calculated from the difference in sound velocity in the two directions. In future versions these calculations may be made in a micro-controller. The instrument has demonstrated a resolution of <0.3% for C3F8/C2F6 mixtures with ~20%C2F6, with simultaneous flow resolution of ~0.1% of F.S. Higher precision is possible: a sensitivity of ~0.005% to leaks of C3F8 into the ATLAS pixel detector nitrogen envelope (mw difference 156) has been seen. The instrument has many applications, including analysis of hydrocarbons, mixtures for semi-conductor manufacture and anesthesia.