ICALEPCS2021 - List of Keywords (FPGA)

Paper	Title	Other Keywords	Page
TUAL02	Development of a Single Cavity Regulation Based on microTCA.4 for SAPS-TP	controls, cavity, hardware, interface	286
	W. Long, X. Li, S.H. Liu IHEP, Beijing, People’s Republic of China Y. Liu DNSC, Dongguan, People’s Republic of China
	A domestic hardware platform based on MTCA.4 is developed for a single cavity regulation in Southern Advanced Photon Source Test Platform (SAPS-TP). A multifunction digital processing Advanced Mezzanine Card (AMC) works as the core function module of the whole system, implement high speed data processing, Low-Level Radio Frequency (LLRF) control algorithm and interlock system. Its core data processing chip is a Xilinx ZYNQ SOC, which is embedded an ARM CPU to implement EPICS IOC under embedded Linux. A down-conversion and up-conversion RTM for cavity probes sensing and high power RF source driver can communi-cate with AMC module by a ZONE3 connector. A hosted tuning control FPGA Mezzanine Card (FMC) combines both the piezo controlling and step-motor controlling functions for independent external drive devices. The design of the hardware and software of the platform electronics and some test results are described in this paper. Further test and optimization is under way.
	Slides TUAL02 [10.504 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUAL02
About •	Received ※ 10 October 2021 Revised ※ 28 November 2021 Accepted ※ 22 December 2021 Issue date ※ 24 January 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAL03	R&D Studies for the Atlas Tile Calorimeter Daughterboard	radiation, detector, electron, electronics	290
	E. Valdes Santurio, K.E. Dunne, S. Lee FYSIKUM, AlbaNova, Stockholm University, Stockholm, Sweden C. Bohm, H. Motzkau, S.B. Silverstein Stockholm University, Stockholm, Sweden
	The ATLAS Hadronic Calorimeter DaughterBoard (DB) interfaces the on-detector with the off-detector electronics. The DB features two 4.6 Gbps downlinks and two pairs of 9.6 Gbps uplinks powered by four SFP+ Optical transceivers. The downlinks receive configuration commands and LHC timing to be propagated to the front-end, and the uplinks transmit continuous high-speed readout of digitized PMT samples, detector control system and monitoring data. The design minimizes single points of failure and mitigates radiation damage by means of a double-redundant scheme. To mitigate Single Event Upset rates, Xilinx Soft Error Mitigation and Triple Mode Redundancy are used. Reliability in the high speed links is achieve by adopting Cyclic Redundancy Check in the uplinks and Forward Error Correction in the downlinks. The DB features a dedicated Single Event Latch-up protection circuitry that power-cycles the board in the case of any over-current event avoiding any possible hardware damages. We present a summary of the studies performed to verify the reliability if the performance of the DB revision 6, and the radiation qualification tests of the components used for the design.
	Slides TUAL03 [4.675 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUAL03
About •	Received ※ 10 October 2021 Revised ※ 20 October 2021 Accepted ※ 22 December 2021 Issue date ※ 03 January 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUPV004	The FPGA-Based Control Architecture, EPICS Interface and Advanced Operational Modes of the High-Dynamic Double-Crystal Monochromator for Sirius/LNLS	controls, undulator, EPICS, operation	370
	R.R. Geraldes, J.L. Brito Neto, E.P. Coelho, L.P. Do Carmo, A.Y. Horita, S.A.L. Luiz, M.A.L. Moraes LNLS, Campinas, Brazil
	Funding: Ministry of Science, Technology and Innovation (MCTI) The High-Dynamic Double-Crystal Monochromator (HD-DCM) has been developed since 2015 at Sirius/LNLS with an innovative high-bandwidth mechatronic architecture to reach the unprecedented target of 10 nrad RMS (1 Hz - 2.5 kHz) in crystals parallelism also during energy fly-scans. After the initial work in Speedgoat’s xPC rapid prototyping platform, for beamline operation the instrument controller was deployed to NI’s CompactRIO (cRIO), as a rugged platform combining FPGA and real-time capabilities. Customized libraries needed to be developed in LabVIEW and a heavily FPGA-based control architecture was required to finally reach a 20 kHz control loop rate. This work summarizes the final control architecture of the HD-DCM, highlighting the main hardware and software challenges; describes its integration with the EPICS control system and user interfaces; and discusses its integration with an undulator source. *Geraldes, R. R., et al. "The status of the new High-Dynamic DCM for Sirius." Proc. MEDSI 2018 (2018).
	Poster TUPV004 [2.549 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUPV004
About •	Received ※ 13 October 2021 Accepted ※ 20 November 2021 Issue date ※ 27 November 2021
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUPV034	Development of an Automated High Temperature Superconductor Coil Winding Machine at CERN	controls, software, GUI, hadron	473
	H. Reymond, M. Dam, A. Haziot, P.D. Jankowski, P.J. Koziol, T.H. Nes, F.O. Pincot, S.C. Richter CERN, Geneva, Switzerland H. Felice LBNL, Berkeley, California, USA
	Within the framework of technology studies on future accelerators, CERN has initiated a five-years R&D project aimed at the evaluation of the REBCO (Rare Earth Barium Copper Oxide) High Temperature Superconductors (HTS). The study covers a number of areas from material science to electromechanical properties. The REBCO high-field tape will be tested on different HTS magnet prototypes, such as HDMS (HTS Demonstrator Magnet for Space), GaToroid (hadron therapy Gantry based on a toroidal magnetic field) and other smaller coils that will be fabricated to study the tape’s potential. To assemble the HTS coils, a new automatic winding station has been designed and constructed at CERN. A touch panel combined with an embedded controller running software developed in-house provides a sophisticated, yet intuitive and user-friendly system aimed at maintaining perfect coil winding conditions. In this paper, we describe the mechanical choices and techniques used to control the seven HTS spool tapes and the winding machine. We also present the analysis of several coils already produced.
	Poster TUPV034 [8.048 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUPV034
About •	Received ※ 07 October 2021 Accepted ※ 15 December 2021 Issue date ※ 21 December 2021
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV028	CompactRIO Custom Module Design for the Beamline’s Control System at Sirius	controls, power-supply, hardware, software	715
	L.S. Perissinotto, F.H. Cardoso, M.M. Donatti LNLS, Campinas, Brazil
	The CompactRIO (cRIO) platform is the standard hardware choice for data acquisition, controls and synchronization tasks at Sirius beamlines. The cRIO controllers are equipped with a processor running a Real-Time Linux and contains an embedded FPGA, that could be programmed using Labview. The platform supports industrial I/O modules for a large variety of signals, sensors, and interfaces. Even with many commercial modules available, complex synchrotron radiation experiments demands customized signal acquisition hardware to achieve proper measurements and control system’s integration. This work aims to describe hardware and software aspects of the first custom 8-channel differential digital I/O module (compatible with RS485/RS422) developed for the Sirius beamlines. The module is compliant with cRIO specification and can perform differential communication with maximum 20 MHz update rate. The features, architecture and its benchmark tests will be presented. This project is part of an effort to expand the use of the cRIO platform in scientific experiments at Sirius and brings the opportunity to increase the expertise to develop custom hardware solutions to cover future applications.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV028
About •	Received ※ 09 October 2021 Revised ※ 21 October 2021 Accepted ※ 27 February 2022 Issue date ※ 01 March 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV031	Status of the uTCA Digital LLRF design for SARAF Phase II	LLRF, controls, cavity, interface	720
	J. Fernández, P. Gil, J.G. Ramirez 7S, Peligros (Granada), Spain G. Desmarchelier CEA-DRF-IRFU, France G. Ferrand, F. Gohier, N. Pichoff CEA-IRFU, Gif-sur-Yvette, France
	One of the crucial control systems of any particle ac-celerator is the Low-Level Radio Frequency (LLRF). The purpose of a LLRF is to control the amplitude and phase of the field inside the accelerating cavity. The LLRF is a subsystem of the CEA (Commissariat à l’Energie Atomique) control domain for the SARAF-LINAC (Soreq Applied Research Accelerator Facility ’ Linear Accelera-tor) instrumentation and Seven Solutions has designed, developed, manufactured, and tested the system based on CEA technical specifications. The final version of this digital LLRF will be installed in the SARAF accelerator in Israel at the end of 2021. The architecture, design, and development as well as the performance of the LLRF system will be presented in this paper. The benefits of the proposed architecture and the first results will be shown.
	Poster WEPV031 [2.607 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV031
About •	Received ※ 08 October 2021 Revised ※ 19 October 2021 Accepted ※ 12 December 2021 Issue date ※ 25 February 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV033	Architecture of a Multi-Channel Data Streaming Device with an FPGA as a Coprocessor	timing, controls, real-time, hardware	724
	J.M. Nogiec, P. Thompson Fermilab, Batavia, Illinois, USA
	Funding: This work was supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics The design of a data acquisition system often involves the integration of a Field Programmable Gate Array (FPGA) with analog front-end components to achieve precise timing and control. Reuse of these hardware systems can be difficult since they need to be tightly coupled to the communications interface and timing requirements of the specific ADC used. A hybrid design exploring the use of FPGA as a coprocessor to a traditional CPU in a dataflow architecture is presented. Reduction in the volume of data and gradual transitioning of data processing away from a hard real-time environment are both discussed. Chief design concerns, including data throughput and precise synchronization with external stimuli, are addressed. The discussion is illustrated by the implementation of a multi-channel digital integrator, a device based entirely on commercial off-the-shelf (COTS) equipment.
	Poster WEPV033 [0.489 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV033
About •	Received ※ 09 October 2021 Accepted ※ 21 November 2021 Issue date ※ 08 December 2021
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV038	Performance Verification of New Machine Protection System Prototype for RIKEN RI Beam Factory	controls, PLC, operation, factory	742
	M. Komiyama, M. Fujimaki, N. Fukunishi, K. Kumagai, A. Uchiyama RIKEN Nishina Center, Wako, Japan M. Hamanaka, T. Nakamura SHI Accelerator Service Ltd., Tokyo, Japan
	We report on performance verification of a prototype of a new machine protection system for the RIKEN Radioactive Isotope Beam Factory (RIBF). This prototype was developed to update a beam interlock system (BIS) in operation since 2006. The new system, like the BIS, is configured using a programmable logic controller (PLC). We applied the prototype to a small part of RIBF and started its operation in Sept., 2020. It consists of two separate PLC stations, and there are 28 digital inputs and 23 analog inputs as interlock signals, and 5 digital outputs are used to stop a beam in total. The observed response time averaged 2 ms and 5.7 ms, respectively, within one station and with both stations. When deploying the prototype in the same scale as the BIS, which consists of 5 PLC stations with roughly 400 signals, the response time is estimated to be over 10 ms, which means that it is too long to protect the equipment when the intensity of the beam accelerated at RIBF becomes higher. Therefore, we are starting to redesign a system by adding a field-programmable gate array (FPGA) to shorten the response time significantly rather than repeating minor improvements to save a few milliseconds.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV038
About •	Received ※ 10 October 2021 Accepted ※ 21 November 2021 Issue date ※ 24 January 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV041	Implementation of a VHDL Application for Interfacing Anybus CompactCom	interface, network, neutron, PLC	755
	S. Gabourin, A. Nordt, S. Pavinato ESS, Lund, Sweden
	The European Spallation Source (ESS ERIC), based in Lund (Sweden), will be in a few years the most powerful neutron source in Europe with an average beam power of 5 MW. It will accelerate proton beam pulses to a Tungsten wheel to generate neutrons by the spallation effect. For such beam, the Machine Protection System (MPS) at ESS must be fast and reliable, and for this reason a Fast Beam Interlock System (FBIS) based on FPGAs is required. Some protection functions monitoring slow values (like temperature, mechanical movements, magnetic fields) need however less strict reaction times and are managed by PLCs. The communications protocol established between PLCs and FBIS is PROFINET fieldbus based. The Anybus CompactCom allows an host to have connectivity to industrial networks as PROFINET. In this context, FBIS represents the host and the application code to interface the AnyBus CompactCom has been fully developed in VHDL. This paper describes an open source implementation to interface a CompactCom M40 with an FPGA.
	Poster WEPV041 [0.967 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV041
About •	Received ※ 09 October 2021 Revised ※ 22 October 2021 Accepted ※ 14 January 2022 Issue date ※ 01 March 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THBR02	White Rabbit and MTCA.4 Use in the LLRF Upgrade for CERN’s SPS	LLRF, controls, cavity, network	847
	T. Włostowski, K. Adrianek, M. Arruat, P. Baudrenghien, A.C. Butterworth, G. Daniluk, J. Egli, J.R. Gill, T. Gingold, J.D. González Cobas, G. Hagmann, P. Kuzmanović, D. Lampridis, M.M. Lipiński, S. Novel González, J.P. Palluel, M. Rizzi, A. Spierer, M. Sumiński, A. Wujek CERN, Geneva, Switzerland
	The Super Proton Synchrotron (SPS) Low-level RF (LLRF) system at CERN was completely revamped in 2020. In the old system, the digital signal processing was clocked by a submultiple of the RF. The new system uses a fixed-frequency clock derived from White Rabbit (WR). This triggered the development of an eRTM module for generating very precise clock signals to be fed to the optional RF backplane in MTCA.4 crates. The eRTM14/15 sandwich of modules implements a WR node delivering clock signals with a jitter below 100 fs. WR-clocked RF synthesis inside the FPGA makes it simple to reproduce the RF elsewhere by broadcasting the frequency-tuning words over the WR network itself. These words are received by the WR2RF-VME module and used to produce beam-synchronous signals such as the bunch clock and the revolution tick. This paper explains the general architecture of this new LLRF system, highlighting the role of WR-based synchronization. It then goes on to describe the hardware and gateware designs for both modules, along with their supporting software. A recount of our experience with the deployment of the MTCA.4 platform is also provided.
	Slides THBR02 [0.981 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THBR02
About •	Received ※ 12 October 2021 Revised ※ 24 October 2021 Accepted ※ 03 January 2022 Issue date ※ 28 February 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPV021	TATU: A Flexible FPGA-Based Trigger and Timer Unit Created on CompactRIO for the First Sirius Beamlines	operation, controls, EPICS, experiment	908
	J.R. Piton, D. Alnajjar, D.H.C. Araujo, J.L. Brito Neto, L.P. Do Carmo, L.C. Guedes, M.A.L. Moraes LNLS, Campinas, Brazil
	In the modern synchrotron light sources, the higher brilliance leads to shorter acquisition times at the experimental stations. For most beamlines of the fourth-generation source SIRIUS, it was imperative to shift from the usual software-based synchronization of operations to the much faster triggering by hardware of some key equipment involved in the experiments. As a basis of their control system for devices, the SIRIUS beamlines have standard CompactRIO controllers and I/O modules along the hutches. Equipped with a FPGA and a hard processor running Linux Real-Time, this platform could deal with the triggers from and to other devices, in the order of ms and µs. TATU (Time and Trigger Unit) is a code running in a CompactRIO unit to coordinate multiple triggering conditions and actions. TATU can be either the master pulse generator or the follower of other signals. Complex trigger pattern generation is set from a user-friendly standardized interface. EPICS process variables (by means of LNLS Nheengatu) are used to set parameters and to follow the execution status. The concept and first field test results in at least four SIRIUS beamlines are presented. D. Alnajjar, G. S. Fedel, and J. R. Piton, "Project Nheengatu: EPICS support for CompactRIO FPGA and LabVIEW-RT", ICALEPCS’19, New York, NY, USA, Oct. 2019, paper WEMPL002.
	Poster THPV021 [0.618 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THPV021
About •	Received ※ 10 October 2021 Accepted ※ 21 November 2021 Issue date ※ 02 February 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Other Keywords

Page

TUAL02

Development of a Single Cavity Regulation Based on microTCA.4 for SAPS-TP

controls, cavity, hardware, interface

286

W. Long, X. Li, S.H. Liu
IHEP, Beijing, People’s Republic of China
Y. Liu
DNSC, Dongguan, People’s Republic of China

A domestic hardware platform based on MTCA.4 is developed for a single cavity regulation in Southern Advanced Photon Source Test Platform (SAPS-TP). A multifunction digital processing Advanced Mezzanine Card (AMC) works as the core function module of the whole system, implement high speed data processing, Low-Level Radio Frequency (LLRF) control algorithm and interlock system. Its core data processing chip is a Xilinx ZYNQ SOC, which is embedded an ARM CPU to implement EPICS IOC under embedded Linux. A down-conversion and up-conversion RTM for cavity probes sensing and high power RF source driver can communi-cate with AMC module by a ZONE3 connector. A hosted tuning control FPGA Mezzanine Card (FMC) combines both the piezo controlling and step-motor controlling functions for independent external drive devices. The design of the hardware and software of the platform electronics and some test results are described in this paper. Further test and optimization is under way.

Slides TUAL02 [10.504 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUAL02

About •

Received ※ 10 October 2021 Revised ※ 28 November 2021 Accepted ※ 22 December 2021 Issue date ※ 24 January 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAL03

R&D Studies for the Atlas Tile Calorimeter Daughterboard

radiation, detector, electron, electronics

290

E. Valdes Santurio, K.E. Dunne, S. Lee
FYSIKUM, AlbaNova, Stockholm University, Stockholm, Sweden
C. Bohm, H. Motzkau, S.B. Silverstein
Stockholm University, Stockholm, Sweden

The ATLAS Hadronic Calorimeter DaughterBoard (DB) interfaces the on-detector with the off-detector electronics. The DB features two 4.6 Gbps downlinks and two pairs of 9.6 Gbps uplinks powered by four SFP+ Optical transceivers. The downlinks receive configuration commands and LHC timing to be propagated to the front-end, and the uplinks transmit continuous high-speed readout of digitized PMT samples, detector control system and monitoring data. The design minimizes single points of failure and mitigates radiation damage by means of a double-redundant scheme. To mitigate Single Event Upset rates, Xilinx Soft Error Mitigation and Triple Mode Redundancy are used. Reliability in the high speed links is achieve by adopting Cyclic Redundancy Check in the uplinks and Forward Error Correction in the downlinks. The DB features a dedicated Single Event Latch-up protection circuitry that power-cycles the board in the case of any over-current event avoiding any possible hardware damages. We present a summary of the studies performed to verify the reliability if the performance of the DB revision 6, and the radiation qualification tests of the components used for the design.

Slides TUAL03 [4.675 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUAL03

About •

Received ※ 10 October 2021 Revised ※ 20 October 2021 Accepted ※ 22 December 2021 Issue date ※ 03 January 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUPV004

The FPGA-Based Control Architecture, EPICS Interface and Advanced Operational Modes of the High-Dynamic Double-Crystal Monochromator for Sirius/LNLS

controls, undulator, EPICS, operation

370

R.R. Geraldes, J.L. Brito Neto, E.P. Coelho, L.P. Do Carmo, A.Y. Horita, S.A.L. Luiz, M.A.L. Moraes
LNLS, Campinas, Brazil

Funding: Ministry of Science, Technology and Innovation (MCTI)
The High-Dynamic Double-Crystal Monochromator (HD-DCM) has been developed since 2015 at Sirius/LNLS with an innovative high-bandwidth mechatronic architecture to reach the unprecedented target of 10 nrad RMS (1 Hz - 2.5 kHz) in crystals parallelism also during energy fly-scans. After the initial work in Speedgoat’s xPC rapid prototyping platform, for beamline operation the instrument controller was deployed to NI’s CompactRIO (cRIO), as a rugged platform combining FPGA and real-time capabilities. Customized libraries needed to be developed in LabVIEW and a heavily FPGA-based control architecture was required to finally reach a 20 kHz control loop rate. This work summarizes the final control architecture of the HD-DCM, highlighting the main hardware and software challenges; describes its integration with the EPICS control system and user interfaces; and discusses its integration with an undulator source.
*Geraldes, R. R., et al. "The status of the new High-Dynamic DCM for Sirius." Proc. MEDSI 2018 (2018).

Poster TUPV004 [2.549 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUPV004

About •

Received ※ 13 October 2021 Accepted ※ 20 November 2021 Issue date ※ 27 November 2021

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUPV034

Development of an Automated High Temperature Superconductor Coil Winding Machine at CERN

controls, software, GUI, hadron

473

H. Reymond, M. Dam, A. Haziot, P.D. Jankowski, P.J. Koziol, T.H. Nes, F.O. Pincot, S.C. Richter
CERN, Geneva, Switzerland
H. Felice
LBNL, Berkeley, California, USA

Within the framework of technology studies on future accelerators, CERN has initiated a five-years R&D project aimed at the evaluation of the REBCO (Rare Earth Barium Copper Oxide) High Temperature Superconductors (HTS). The study covers a number of areas from material science to electromechanical properties. The REBCO high-field tape will be tested on different HTS magnet prototypes, such as HDMS (HTS Demonstrator Magnet for Space), GaToroid (hadron therapy Gantry based on a toroidal magnetic field) and other smaller coils that will be fabricated to study the tape’s potential. To assemble the HTS coils, a new automatic winding station has been designed and constructed at CERN. A touch panel combined with an embedded controller running software developed in-house provides a sophisticated, yet intuitive and user-friendly system aimed at maintaining perfect coil winding conditions. In this paper, we describe the mechanical choices and techniques used to control the seven HTS spool tapes and the winding machine. We also present the analysis of several coils already produced.

Poster TUPV034 [8.048 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUPV034

About •

Received ※ 07 October 2021 Accepted ※ 15 December 2021 Issue date ※ 21 December 2021

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV028

CompactRIO Custom Module Design for the Beamline’s Control System at Sirius

controls, power-supply, hardware, software

715

L.S. Perissinotto, F.H. Cardoso, M.M. Donatti
LNLS, Campinas, Brazil

The CompactRIO (cRIO) platform is the standard hardware choice for data acquisition, controls and synchronization tasks at Sirius beamlines. The cRIO controllers are equipped with a processor running a Real-Time Linux and contains an embedded FPGA, that could be programmed using Labview. The platform supports industrial I/O modules for a large variety of signals, sensors, and interfaces. Even with many commercial modules available, complex synchrotron radiation experiments demands customized signal acquisition hardware to achieve proper measurements and control system’s integration. This work aims to describe hardware and software aspects of the first custom 8-channel differential digital I/O module (compatible with RS485/RS422) developed for the Sirius beamlines. The module is compliant with cRIO specification and can perform differential communication with maximum 20 MHz update rate. The features, architecture and its benchmark tests will be presented. This project is part of an effort to expand the use of the cRIO platform in scientific experiments at Sirius and brings the opportunity to increase the expertise to develop custom hardware solutions to cover future applications.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV028

About •

Received ※ 09 October 2021 Revised ※ 21 October 2021 Accepted ※ 27 February 2022 Issue date ※ 01 March 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV031

Status of the uTCA Digital LLRF design for SARAF Phase II

LLRF, controls, cavity, interface

720

J. Fernández, P. Gil, J.G. Ramirez
7S, Peligros (Granada), Spain
G. Desmarchelier
CEA-DRF-IRFU, France
G. Ferrand, F. Gohier, N. Pichoff
CEA-IRFU, Gif-sur-Yvette, France

One of the crucial control systems of any particle ac-celerator is the Low-Level Radio Frequency (LLRF). The purpose of a LLRF is to control the amplitude and phase of the field inside the accelerating cavity. The LLRF is a subsystem of the CEA (Commissariat à l’Energie Atomique) control domain for the SARAF-LINAC (Soreq Applied Research Accelerator Facility ’ Linear Accelera-tor) instrumentation and Seven Solutions has designed, developed, manufactured, and tested the system based on CEA technical specifications. The final version of this digital LLRF will be installed in the SARAF accelerator in Israel at the end of 2021. The architecture, design, and development as well as the performance of the LLRF system will be presented in this paper. The benefits of the proposed architecture and the first results will be shown.

Poster WEPV031 [2.607 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV031

About •

Received ※ 08 October 2021 Revised ※ 19 October 2021 Accepted ※ 12 December 2021 Issue date ※ 25 February 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV033

Architecture of a Multi-Channel Data Streaming Device with an FPGA as a Coprocessor

timing, controls, real-time, hardware

724

J.M. Nogiec, P. Thompson
Fermilab, Batavia, Illinois, USA

Funding: This work was supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics
The design of a data acquisition system often involves the integration of a Field Programmable Gate Array (FPGA) with analog front-end components to achieve precise timing and control. Reuse of these hardware systems can be difficult since they need to be tightly coupled to the communications interface and timing requirements of the specific ADC used. A hybrid design exploring the use of FPGA as a coprocessor to a traditional CPU in a dataflow architecture is presented. Reduction in the volume of data and gradual transitioning of data processing away from a hard real-time environment are both discussed. Chief design concerns, including data throughput and precise synchronization with external stimuli, are addressed. The discussion is illustrated by the implementation of a multi-channel digital integrator, a device based entirely on commercial off-the-shelf (COTS) equipment.

Poster WEPV033 [0.489 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV033

About •

Received ※ 09 October 2021 Accepted ※ 21 November 2021 Issue date ※ 08 December 2021

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPV038

Performance Verification of New Machine Protection System Prototype for RIKEN RI Beam Factory

controls, PLC, operation, factory

742

M. Komiyama, M. Fujimaki, N. Fukunishi, K. Kumagai, A. Uchiyama
RIKEN Nishina Center, Wako, Japan
M. Hamanaka, T. Nakamura
SHI Accelerator Service Ltd., Tokyo, Japan

We report on performance verification of a prototype of a new machine protection system for the RIKEN Radioactive Isotope Beam Factory (RIBF). This prototype was developed to update a beam interlock system (BIS) in operation since 2006. The new system, like the BIS, is configured using a programmable logic controller (PLC). We applied the prototype to a small part of RIBF and started its operation in Sept., 2020. It consists of two separate PLC stations, and there are 28 digital inputs and 23 analog inputs as interlock signals, and 5 digital outputs are used to stop a beam in total. The observed response time averaged 2 ms and 5.7 ms, respectively, within one station and with both stations. When deploying the prototype in the same scale as the BIS, which consists of 5 PLC stations with roughly 400 signals, the response time is estimated to be over 10 ms, which means that it is too long to protect the equipment when the intensity of the beam accelerated at RIBF becomes higher. Therefore, we are starting to redesign a system by adding a field-programmable gate array (FPGA) to shorten the response time significantly rather than repeating minor improvements to save a few milliseconds.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV038

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Received ※ 10 October 2021 Accepted ※ 21 November 2021 Issue date ※ 24 January 2022

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WEPV041

Implementation of a VHDL Application for Interfacing Anybus CompactCom

interface, network, neutron, PLC

755

S. Gabourin, A. Nordt, S. Pavinato
ESS, Lund, Sweden

The European Spallation Source (ESS ERIC), based in Lund (Sweden), will be in a few years the most powerful neutron source in Europe with an average beam power of 5 MW. It will accelerate proton beam pulses to a Tungsten wheel to generate neutrons by the spallation effect. For such beam, the Machine Protection System (MPS) at ESS must be fast and reliable, and for this reason a Fast Beam Interlock System (FBIS) based on FPGAs is required. Some protection functions monitoring slow values (like temperature, mechanical movements, magnetic fields) need however less strict reaction times and are managed by PLCs. The communications protocol established between PLCs and FBIS is PROFINET fieldbus based. The Anybus CompactCom allows an host to have connectivity to industrial networks as PROFINET. In this context, FBIS represents the host and the application code to interface the AnyBus CompactCom has been fully developed in VHDL. This paper describes an open source implementation to interface a CompactCom M40 with an FPGA.

Poster WEPV041 [0.967 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV041

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Received ※ 09 October 2021 Revised ※ 22 October 2021 Accepted ※ 14 January 2022 Issue date ※ 01 March 2022

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THBR02

White Rabbit and MTCA.4 Use in the LLRF Upgrade for CERN’s SPS

LLRF, controls, cavity, network

847

T. Włostowski, K. Adrianek, M. Arruat, P. Baudrenghien, A.C. Butterworth, G. Daniluk, J. Egli, J.R. Gill, T. Gingold, J.D. González Cobas, G. Hagmann, P. Kuzmanović, D. Lampridis, M.M. Lipiński, S. Novel González, J.P. Palluel, M. Rizzi, A. Spierer, M. Sumiński, A. Wujek
CERN, Geneva, Switzerland

The Super Proton Synchrotron (SPS) Low-level RF (LLRF) system at CERN was completely revamped in 2020. In the old system, the digital signal processing was clocked by a submultiple of the RF. The new system uses a fixed-frequency clock derived from White Rabbit (WR). This triggered the development of an eRTM module for generating very precise clock signals to be fed to the optional RF backplane in MTCA.4 crates. The eRTM14/15 sandwich of modules implements a WR node delivering clock signals with a jitter below 100 fs. WR-clocked RF synthesis inside the FPGA makes it simple to reproduce the RF elsewhere by broadcasting the frequency-tuning words over the WR network itself. These words are received by the WR2RF-VME module and used to produce beam-synchronous signals such as the bunch clock and the revolution tick. This paper explains the general architecture of this new LLRF system, highlighting the role of WR-based synchronization. It then goes on to describe the hardware and gateware designs for both modules, along with their supporting software. A recount of our experience with the deployment of the MTCA.4 platform is also provided.

Slides THBR02 [0.981 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THBR02

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Received ※ 12 October 2021 Revised ※ 24 October 2021 Accepted ※ 03 January 2022 Issue date ※ 28 February 2022

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THPV021

TATU: A Flexible FPGA-Based Trigger and Timer Unit Created on CompactRIO for the First Sirius Beamlines

operation, controls, EPICS, experiment

908

J.R. Piton, D. Alnajjar, D.H.C. Araujo, J.L. Brito Neto, L.P. Do Carmo, L.C. Guedes, M.A.L. Moraes
LNLS, Campinas, Brazil

In the modern synchrotron light sources, the higher brilliance leads to shorter acquisition times at the experimental stations. For most beamlines of the fourth-generation source SIRIUS, it was imperative to shift from the usual software-based synchronization of operations to the much faster triggering by hardware of some key equipment involved in the experiments. As a basis of their control system for devices, the SIRIUS beamlines have standard CompactRIO controllers and I/O modules along the hutches. Equipped with a FPGA and a hard processor running Linux Real-Time, this platform could deal with the triggers from and to other devices, in the order of ms and µs. TATU (Time and Trigger Unit) is a code running in a CompactRIO unit to coordinate multiple triggering conditions and actions. TATU can be either the master pulse generator or the follower of other signals. Complex trigger pattern generation is set from a user-friendly standardized interface. EPICS process variables (by means of LNLS Nheengatu*) are used to set parameters and to follow the execution status. The concept and first field test results in at least four SIRIUS beamlines are presented.
* D. Alnajjar, G. S. Fedel, and J. R. Piton, "Project Nheengatu: EPICS support for CompactRIO FPGA and LabVIEW-RT", ICALEPCS’19, New York, NY, USA, Oct. 2019, paper WEMPL002.

Poster THPV021 [0.618 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THPV021

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Received ※ 10 October 2021 Accepted ※ 21 November 2021 Issue date ※ 02 February 2022

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