Keyword: LLRF
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MOPV001 Status of the SARAF-Phase2 Control System controls, EPICS, cryomodule, network 93
  • F. Gougnaud, P. Bargueden, G. Desmarchelier, A. Gaget, P. Guiho, A. Lotode, Y. Mariette, V. Nadot, N. Solenne
    CEA-DRF-IRFU, France
  • D. Darde, G. Ferrand, F. Gohier, T.J. Joannem, G. Monnereau, V. Silva
    CEA-IRFU, Gif-sur-Yvette, France
  • H. Isakov, A. Perry, E. Reinfeld, I. Shmuely, Y. Solomon, N. Tamim
    Soreq NRC, Yavne, Israel
  • T. Zchut
    CEA LIST, Palaiseau, France
  SNRC and CEA collaborate to the upgrade of the SARAF accelerator to 5 mA CW 40 Mev deuteron and proton beams and also closely to the control system. CEA is in charge of the Control System (including cabinets) design and implementation for the Injector (upgrade), MEBT and Super Conducting Linac made up of 4 cryomodules hosting HWR cavities and solenoid packages. This paper gives a detailed presentation of the control system architecture from hardware and EPICS software points of view. The hardware standardization relies on MTCA.4 that is used for LLRF, BPM, BLM and FC controls and on Siemens PLC 1500 series for vacuum, cryogenics and interlock. CEA IRFU EPICS Environment (IEE) platform is used for the whole accelerator. IEE is based on virtual machines and our MTCA.4 solutions and enables us to have homogenous EPICS modules. It also provides a development and production workflow. SNRC has integrated IEE into a new IT network based on advanced technology. The commissioning is planned to start late summer 2021.  
poster icon Poster MOPV001 [1.787 MB]  
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About • Received ※ 09 October 2021       Revised ※ 20 October 2021       Accepted ※ 03 November 2021       Issue date ※ 11 March 2022
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TUPV010 Integration of OPC UA at ELBE controls, PLC, SCADA, interface 400
  • K. Zenker, M. Kuntzsch, R. Steinbrück
    HZDR, Dresden, Germany
  The Electron Linac for beams with high Brilliance and low Emittance (ELBE) at Helmholtz-Zentrum Dresden-Rossendorf (HZDR) is in operation since 2001. It is operated using the SCADA system WinCC by Siemens. The majority of ELBE systems is connected to WinCC via industrial Ethernet and proprietary S7 communication. However, in recent years new subsystems had to be integrated into the existing infrastructure, which do not provide S7 communication interfaces. Instead, OPC UA has been chosen for system integration. We will show how we use OPC UA as a common communication layer between industrial and scientific instruments as well as proprietary and open source control system software. For example, OPC UA support has been implemented for the ChimeraTK framework developed at DESY. ChimeraTK is used at ELBE e.g. for integrating MicroTCA.4 based subsystems like the digital LLRF system. Furthermore, we are developing a machine data interface for ELBE users. In combination with a certification authority, which hands out user certificates for data access, external users can gain read and write access to different ELBE subsystem data provided by a single OPC UA server.  
DOI • reference for this paper ※  
About • Received ※ 08 October 2021       Accepted ※ 20 November 2021       Issue date ※ 15 December 2021  
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WEPV031 Status of the uTCA Digital LLRF design for SARAF Phase II controls, cavity, FPGA, interface 720
  • J. Fernández, P. Gil, J.G. Ramirez
    7S, Peligros (Granada), Spain
  • G. Desmarchelier
    CEA-DRF-IRFU, France
  • G. Ferrand, F. Gohier, N. Pichoff
    CEA-IRFU, Gif-sur-Yvette, France
  One of the crucial control systems of any particle ac-celerator is the Low-Level Radio Frequency (LLRF). The purpose of a LLRF is to control the amplitude and phase of the field inside the accelerating cavity. The LLRF is a subsystem of the CEA (Commissariat à l’Energie Atomique) control domain for the SARAF-LINAC (Soreq Applied Research Accelerator Facility ’ Linear Accelera-tor) instrumentation and Seven Solutions has designed, developed, manufactured, and tested the system based on CEA technical specifications. The final version of this digital LLRF will be installed in the SARAF accelerator in Israel at the end of 2021. The architecture, design, and development as well as the performance of the LLRF system will be presented in this paper. The benefits of the proposed architecture and the first results will be shown.  
poster icon Poster WEPV031 [2.607 MB]  
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About • Received ※ 08 October 2021       Revised ※ 19 October 2021       Accepted ※ 12 December 2021       Issue date ※ 25 February 2022
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THBR02 White Rabbit and MTCA.4 Use in the LLRF Upgrade for CERN’s SPS controls, FPGA, cavity, network 847
  • T. Włostowski, K. Adrianek, M. Arruat, P. Baudrenghien, A.C. Butterworth, G. Daniluk, J. Egli, J.R. Gill, T. Gingold, J.D. González Cobas, G. Hagmann, P. Kuzmanović, D. Lampridis, M.M. Lipiński, S. Novel González, J.P. Palluel, M. Rizzi, A. Spierer, M. Sumiński, A. Wujek
    CERN, Geneva, Switzerland
  The Super Proton Synchrotron (SPS) Low-level RF (LLRF) system at CERN was completely revamped in 2020. In the old system, the digital signal processing was clocked by a submultiple of the RF. The new system uses a fixed-frequency clock derived from White Rabbit (WR). This triggered the development of an eRTM module for generating very precise clock signals to be fed to the optional RF backplane in MTCA.4 crates. The eRTM14/15 sandwich of modules implements a WR node delivering clock signals with a jitter below 100 fs. WR-clocked RF synthesis inside the FPGA makes it simple to reproduce the RF elsewhere by broadcasting the frequency-tuning words over the WR network itself. These words are received by the WR2RF-VME module and used to produce beam-synchronous signals such as the bunch clock and the revolution tick. This paper explains the general architecture of this new LLRF system, highlighting the role of WR-based synchronization. It then goes on to describe the hardware and gateware designs for both modules, along with their supporting software. A recount of our experience with the deployment of the MTCA.4 platform is also provided.  
slides icon Slides THBR02 [0.981 MB]  
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About • Received ※ 12 October 2021       Revised ※ 24 October 2021       Accepted ※ 03 January 2022       Issue date ※ 28 February 2022
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THPV029 Development of Timing Read-Back System for Stable Operation of J-PARC timing, operation, proton, controls 927
  • M. Yang
    Sokendai, Ibaraki, Japan
  • N. Kamikubota
    KEK, Ibaraki, Japan
  • N. Kikuzawa
    JAEA/J-PARC, Tokai-mura, Japan
  • K.C. Sato
    J-PARC, KEK & JAEA, Ibaraki-ken, Japan
  • Y. Tajima
    Kanto Information Service (KIS), Accelerator Group, Ibaraki, Japan
  Since 2006, the Japan Proton Accelerator Research Complex (J-PARC) timing system has been operated successfully. However, there were some unexpected trig-ger-failure events, typically missing trigger events, during the operation over 15 years. When a trigger-failure event occurred, it was often tough to find the one with the fault among many suspected modules. To solve the problem more easily, a unique device, triggered scaler, was devel-oped for reading back accelerator signals. The performance of the module has been evaluated in 2018. In 2021, we measured and observed an LLRF sig-nal as the first signal of the read-back system for beam operation. After firmware upgrades of the module, some customized timing read-back systems were developed, and successfully demonstrated as coping strategies for past trigger-failure events. In addition, a future plan to apply the read-back system to other facilities is discussed. More details are given in the paper.  
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About • Received ※ 20 October 2021       Accepted ※ 21 November 2021       Issue date ※ 13 January 2022  
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