Hardware Technology
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CompactPCI-Serial Hardware Toolbox for SLS 2.0  
  • B. Kalantari, E. Johansen, W. Koprek, P. Pollet, G. Theidel
    PSI, Villigen PSI, Switzerland
  Motivated by upcoming large upgrade projects at PSI, most prominently SLS2.0, and due to increasing demands for performance (handling more data, faster processing) in various subsystems of the accelerator and beamlines, our electronics and control system experts had the task to evaluate alternatives to the existing VME technology and build a new portfolio of electronic hardware tools accordingly. CompactPCI-Serial was chosen as the standard platform for building our future modular control and data acquisition systems. We are currently developing two CompactPCI-Serial FPGA boards: FMC+ carrier and the COM-I/O. Both cards use the same family of Xilinx MPSoC (Zynq UltraScale+) as their processing building block. Combination of these two boards, together with COTS hardware should provide our system architects with enough flexibility to build systems with required budget and performance (high-end and/or low-cost) for various applications. We report on the state of the current challenging developments and describe system architectures for building high performance control and data acquisition systems using our hardware toolbox.  
slides icon Slides TUAL01 [23.886 MB]  
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TUAL02 Development of a Single Cavity Regulation Based on microTCA.4 for SAPS-TP 286
  • W. Long, X. Li, S.H. Liu
    IHEP, Beijing, People’s Republic of China
  • Y. Liu
    DNSC, Dongguan, People’s Republic of China
  A domestic hardware platform based on MTCA.4 is developed for a single cavity regulation in Southern Advanced Photon Source Test Platform (SAPS-TP). A multifunction digital processing Advanced Mezzanine Card (AMC) works as the core function module of the whole system, implement high speed data processing, Low-Level Radio Frequency (LLRF) control algorithm and interlock system. Its core data processing chip is a Xilinx ZYNQ SOC, which is embedded an ARM CPU to implement EPICS IOC under embedded Linux. A down-conversion and up-conversion RTM for cavity probes sensing and high power RF source driver can communi-cate with AMC module by a ZONE3 connector. A hosted tuning control FPGA Mezzanine Card (FMC) combines both the piezo controlling and step-motor controlling functions for independent external drive devices. The design of the hardware and software of the platform electronics and some test results are described in this paper. Further test and optimization is under way.  
slides icon Slides TUAL02 [10.504 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUAL02  
About • Received ※ 10 October 2021       Revised ※ 28 November 2021       Accepted ※ 22 December 2021       Issue date ※ 24 January 2022
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TUAL03 R&D Studies for the Atlas Tile Calorimeter Daughterboard 290
  • E. Valdes Santurio, K.E. Dunne, S. Lee
    FYSIKUM, AlbaNova, Stockholm University, Stockholm, Sweden
  • C. Bohm, H. Motzkau, S.B. Silverstein
    Stockholm University, Stockholm, Sweden
  The ATLAS Hadronic Calorimeter DaughterBoard (DB) interfaces the on-detector with the off-detector electronics. The DB features two 4.6 Gbps downlinks and two pairs of 9.6 Gbps uplinks powered by four SFP+ Optical transceivers. The downlinks receive configuration commands and LHC timing to be propagated to the front-end, and the uplinks transmit continuous high-speed readout of digitized PMT samples, detector control system and monitoring data. The design minimizes single points of failure and mitigates radiation damage by means of a double-redundant scheme. To mitigate Single Event Upset rates, Xilinx Soft Error Mitigation and Triple Mode Redundancy are used. Reliability in the high speed links is achieve by adopting Cyclic Redundancy Check in the uplinks and Forward Error Correction in the downlinks. The DB features a dedicated Single Event Latch-up protection circuitry that power-cycles the board in the case of any over-current event avoiding any possible hardware damages. We present a summary of the studies performed to verify the reliability if the performance of the DB revision 6, and the radiation qualification tests of the components used for the design.  
slides icon Slides TUAL03 [4.675 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-TUAL03  
About • Received ※ 10 October 2021       Revised ※ 20 October 2021       Accepted ※ 22 December 2021       Issue date ※ 03 January 2022
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WEPV026 Multi-Channel Heaters Driver for Sirius Beamline’s Optical Devices 705
  • M.M. Donatti, D.H.C. Araujo, F.H. Cardoso, G.B.Z.L. Moreno, L. Sanfelici, G.T. Semissatto
    LNLS, Campinas, Brazil
  Thermal management of optomechanical devices, such as mirrors and monochromators, is one of the main bottlenecks in the overall performance of many X-Rays beamlines, particularly for Sirius: the new 4th generation Brazilian synchrotron light source. Due to high intensity photon beams some optical devices need to be cryogenically cooled and a closed-loop temperature control must be implemented to reduce mechanical distortions and instabilities. This work aims to describe the hardware design of a multi-channel driver for vacuum-ready ohmic heaters used in critical optical elements. The device receives PWM signals and can control up to 8 heaters individually. Interlocks and failure management can be implemented using digital signals input/outputs. The driver is equipped with a software programmable current limiter to prevent load overheating and it has voltage/current diagnostics monitored via EPICS or an embedded HTTP server. Enclosed in a 1U rack mount case, the driver can deliver up to 2A per channel in 12V and 24V output voltage versions. Performance measurements will be presented to evaluate functionalities, noise, linearity and bandwidth response.  
poster icon Poster WEPV026 [2.174 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV026  
About • Received ※ 09 October 2021       Accepted ※ 21 November 2021       Issue date ※ 06 December 2021  
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WEPV027 Expandable and Modular Monitoring and Actuation System for Engineering Cabinets at Sirius Light Source 710
  • P.H. Nallin, J.G.R.S. Franco, R.W. Polli
    LNLS, Campinas, Brazil
  • G.F. Freitas
    CNPEM, Campinas, SP, Brazil
  Having multipurpose hardware architectures for controls and monitoring systems has become a need nowadays. When it comes to modular and easy expandable devices, it brings together a system which is easy to maintain and can reach many applications. Concerning Sirius accelerators, which is a 4th generation light source, monitoring environment variables becomes crucial when it comes to accelerator stability and reliability. Several cabinets take part of engineering infrastructure and monitoring and acting over their environment such as internal temperature, pressure and fan status, increases overall system reliability. This paper presents a non-expensive hardware topology to deal with multiple sensors and actuators mainly designed to monitor cabinets and prevent beam quality loss due to equipment faults.  
poster icon Poster WEPV027 [0.830 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV027  
About • Received ※ 01 October 2021       Revised ※ 09 November 2021       Accepted ※ 21 November 2021       Issue date ※ 28 November 2021
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WEPV028 CompactRIO Custom Module Design for the Beamline’s Control System at Sirius 715
  • L.S. Perissinotto, F.H. Cardoso, M.M. Donatti
    LNLS, Campinas, Brazil
  The CompactRIO (cRIO) platform is the standard hardware choice for data acquisition, controls and synchronization tasks at Sirius beamlines. The cRIO controllers are equipped with a processor running a Real-Time Linux and contains an embedded FPGA, that could be programmed using Labview. The platform supports industrial I/O modules for a large variety of signals, sensors, and interfaces. Even with many commercial modules available, complex synchrotron radiation experiments demands customized signal acquisition hardware to achieve proper measurements and control system’s integration. This work aims to describe hardware and software aspects of the first custom 8-channel differential digital I/O module (compatible with RS485/RS422) developed for the Sirius beamlines. The module is compliant with cRIO specification and can perform differential communication with maximum 20 MHz update rate. The features, architecture and its benchmark tests will be presented. This project is part of an effort to expand the use of the cRIO platform in scientific experiments at Sirius and brings the opportunity to increase the expertise to develop custom hardware solutions to cover future applications.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV028  
About • Received ※ 09 October 2021       Revised ※ 21 October 2021       Accepted ※ 27 February 2022       Issue date ※ 01 March 2022
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Testing of the RTM Carrier Boards for the ESS Accelerator  
  • J. Szewiński, P.R. Bartoszek, K. Chmielewski, K. Kostrzewa, T. Kowalski, P. Markowski, D. Rybka, M. Sitek, Z. Wojciechowski
    NCBJ, Świerk/Otwock, Poland
  As a part of Polish in-kind contribution to the European Spallation Source (ESS), National Centre for Nuclear Research has developed low cost AMC board, which is used in the MTCA based ESS LLRF system to support RTM units in the crate. Board due to its primary function has been called ’RTM Carrier’, which may be confusing, because it is an AMC. The low cost board, that by concept shall be simple, without own functionality except providing PCIe access from MTCA backplane to the RTM device, has required significant amount of work to create complete firmware and software to cover all board functionality, which was needed to perform factory acceptance tests (FAT) of the described boards. This contribution will describe structure of the FPGA firmware and software used for the RTM Carrier acceptance testing, including techniques used for testing individual functions and features of the board.  
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WEPV031 Status of the uTCA Digital LLRF design for SARAF Phase II 720
  • J. Fernández, P. Gil, J.G. Ramirez
    7S, Peligros (Granada), Spain
  • G. Desmarchelier
    CEA-DRF-IRFU, France
  • G. Ferrand, F. Gohier, N. Pichoff
    CEA-IRFU, Gif-sur-Yvette, France
  One of the crucial control systems of any particle ac-celerator is the Low-Level Radio Frequency (LLRF). The purpose of a LLRF is to control the amplitude and phase of the field inside the accelerating cavity. The LLRF is a subsystem of the CEA (Commissariat à l’Energie Atomique) control domain for the SARAF-LINAC (Soreq Applied Research Accelerator Facility ’ Linear Accelera-tor) instrumentation and Seven Solutions has designed, developed, manufactured, and tested the system based on CEA technical specifications. The final version of this digital LLRF will be installed in the SARAF accelerator in Israel at the end of 2021. The architecture, design, and development as well as the performance of the LLRF system will be presented in this paper. The benefits of the proposed architecture and the first results will be shown.  
poster icon Poster WEPV031 [2.607 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV031  
About • Received ※ 08 October 2021       Revised ※ 19 October 2021       Accepted ※ 12 December 2021       Issue date ※ 25 February 2022
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WEPV033 Architecture of a Multi-Channel Data Streaming Device with an FPGA as a Coprocessor 724
  • J.M. Nogiec, P. Thompson
    Fermilab, Batavia, Illinois, USA
  Funding: This work was supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics
The design of a data acquisition system often involves the integration of a Field Programmable Gate Array (FPGA) with analog front-end components to achieve precise timing and control. Reuse of these hardware systems can be difficult since they need to be tightly coupled to the communications interface and timing requirements of the specific ADC used. A hybrid design exploring the use of FPGA as a coprocessor to a traditional CPU in a dataflow architecture is presented. Reduction in the volume of data and gradual transitioning of data processing away from a hard real-time environment are both discussed. Chief design concerns, including data throughput and precise synchronization with external stimuli, are addressed. The discussion is illustrated by the implementation of a multi-channel digital integrator, a device based entirely on commercial off-the-shelf (COTS) equipment.
poster icon Poster WEPV033 [0.489 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-WEPV033  
About • Received ※ 09 October 2021       Accepted ※ 21 November 2021       Issue date ※ 08 December 2021  
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