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BiBTeX citation export for WEPV030: Testing of the RTM Carrier Boards for the ESS Accelerator

@unpublished{szewinski:icalepcs2021-wepv030,
  author       = {J. Szewiński and P.R. Bartoszek and K. Chmielewski and K. Kostrzewa and T. Kowalski and P. Markowski and D. Rybka and M. Sitek and Z. Wojciechowski},
% author       = {J. Szewiński and P.R. Bartoszek and K. Chmielewski and K. Kostrzewa and T. Kowalski and P. Markowski and others},
% author       = {J. Szewiński and others},
  title        = {{Testing of the RTM Carrier Boards for the ESS Accelerator}},
  booktitle    = {Proc. ICALEPCS'21},
  language     = {english},
  intype       = {presented at the},
  series       = {International Conference on Accelerator and Large Experimental Physics Control Systems},
  number       = {18},
  venue        = {Shanghai, China},
  publisher    = {JACoW Publishing, Geneva, Switzerland},
  month        = {03},
  year         = {2022},
  note         = {presented at ICALEPCS'21 in Shanghai, China, unpublished},
  abstract     = {{As a part of Polish in-kind contribution to the European Spallation Source (ESS), National Centre for Nuclear Research has developed low cost AMC board, which is used in the MTCA based ESS LLRF system to support RTM units in the crate. Board due to its primary function has been called ’RTM Carrier’, which may be confusing, because it is an AMC. The low cost board, that by concept shall be simple, without own functionality except providing PCIe access from MTCA backplane to the RTM device, has required significant amount of work to create complete firmware and software to cover all board functionality, which was needed to perform factory acceptance tests (FAT) of the described boards. This contribution will describe structure of the FPGA firmware and software used for the RTM Carrier acceptance testing, including techniques used for testing individual functions and features of the board.}},
}