Hardware Technology

Paper Title Page
WPPB01 CTF3 Beam Position Monitor Acquisition System 395
 
  • L. P. Bellier, J. N. Jacquemier
    IN2P3-LAPP, Annecy-le-Vieux
  • L. Soby, S. Deghaye
    CERN, Geneva
  
  The CLIC Test Facility 3 (CTF3) is an R&D machine being built to validate concepts that will be used for the Compact Linear Collider (CLIC). Because CTF3 is an instrumentation-intensive machine, a considerable amount of money is put into the acquisition hardware and high-quality cables used to bring the instrument signals to the digitalization crates with as little degradation as possible. The main idea of this new approach is to reduce the distance between the signal source and the A/D conversion, reducing the cost of the cabling. To achieve that, we have developed a radiation hard front-end that we install directly into the accelerator tunnel. This front-end deals with the digitalization of the signals after an analog buffering. Afterwards, the data are sent to a computer through the SPECS field bus. Finally, the digitalized signals are made available to the operation crew thanks to a server implementing the OASIS (Open Analogue Signal Information System) interfaces in the CERN Front-End Software Architecture (FESA). After a presentation of this low-cost solution to BPM acquisition, the paper gives the results of the first integration tests performed in the CTF3 machine.  
WPPB02 The LHC Central Timing Hardware Implementation 400
 
  • J. H. Lewis, J. Serrano, P. Alvarez
    CERN, Geneva
  
  The LHC central timing requirements are very different from those of the injector chain. Not only is machine's safety and reliability critical, but there are other important differences that have forced a new approach. Unlike the injector chain, the LHC processes cannot be usefully broken up into basic time periods and cycles; rather, they are independent, asynchronous, and of arbitrary duration. This paper presents the hardware and low-level software solutions we adopted and the technologies we used to implement them—in particular, the use of reflective memory, reliable use of the global positioning system as a precise time reference, redundancy, transmission-time calibration, safe beam parameter distribution, and the multitasking event generation hardware we developed to control the LHC machine processes.  
WPPB04 Convergence Computer–Communication Methods for Advanced High-Performance Control System 406
 
  • V. I. Vinogradov
    RAS/INR, Moscow
  
  Based on analysis of advanced computer and communication system architectures, a future control system approach is proposed and discussed in this paper. Convergence computer and communication technologies are moving to high-performance modular system architectures on the basis of high-speed switched interconnections. Multicore processors become more perspective ways to high-performance systems, and traditional parallel bus system architectures are extended by higher-speed serial switched interconnections. Compact modular system on the base of passive 3-4 slots PCI bas with fast switch network interconnection are described as examples of a modern, scalable control system solution, which can be compatible extended to advanced system architecture on the basis of new technologies (ATCA,μTCA). Kombi wired and wireless subnets can be used as effective platforms also for large experimental physics control systems and complex computer automation in an experimental area with human interactions inside systems by IP-phones.  
WPPB06 Synchronization System of Synchrotron SOLEIL 409
 
  • P. Betinelli, L. Cassinari, J.-M. Filhol, B. Gagey, F. Langlois, A. Loulergue, J. P. Ricaud
    SOLEIL, Gif-sur-Yvette
  
  To bring electrons from the LINAC to the storage ring, much equipment must be triggered synchronously to the beam. The timing system provides the time base needed for this purpose. More than a simple clocks distribution system, it is a real network, broadcasting clocks and data all over the synchrotron. Data are used to send events to equipment: for example, injection of electrons inside the booster, extraction of electrons from the booster to the storage ring, or even triggering diagnostic equipment. The timing system is made up of a standalone CENTRAL system and several cPCI LOCAL boards. The CENTRAL system provides clocks and data and broadcasts them to the LOCAL boards through an optical fiber network. LOCAL boards are placed close to the equipment, and they provide delayed signals to trigger them. These delays can be precisely adjusted by the user, making the equipment synchronous with the electron beam. After a brief explanation of our needs, the presentation describes the timing systems (architecture, performance, etc.) used at SOLEIL. It also describes the results after a year of use: the good, the bad, and the truth (well, maybe).  
WPPB12 High-Speed X-ray Imaging at NSLS 424
 
  • D. P. Siddons, S. K. Feng
    BNL, Upton, Long Island, New York
  
  We describe two projects currently underway at National Synchrotron Light Source (NSLS). The first is an inexpensive yet high-performance image acquisition system utilizing a low-cost firewire camera, a PMC firewire interface board, EPICS and the in-house written RTEMS-mvme5500 Board Support Package. The BSP, EPICS/RTEMS software and firewire drivers demonstrate a high throughput of image display for the 1024x768x8bit mode of 30 frames per second (fps) of data transfer, while triggering EPICS display at 30 Hz simultaneously. The second is the readout system for the LCLS X-ray Active Matrix Pixel Sensor (XAMPS) detector. The specification of the detector readout requires a 1024x1024x14bit image to be stored to disk at 120 Hz, an average data rate of 252 Mega Bytes/sec. A faster SBC was chosen to be interfaced with a FPGA based PMC card and Fiber Channel storage system. This cost-effective prototype will function efficiently and reliably as a data acquisition system for the implementation of the XAMPS detector developed at the NSLS. Modern software and the use of commercial hardware technology has cut our cost of both systems, and delivered excellent performance.  
WPPB13 Development of Flexible and Logic-Reconfigurable VME Boards 427
 
  • T. Kudo, T. Ohata, T. Hirono
    JASRI/SPring-8, Hyogo-ken
  
  We developed a logic-reconfigurable VME board with high flexibility. The board has two parts, a base board and two IO daughter boards. The base board has a field programmable gate arrays (FPGA) chip for execution of user logic, such as a digital low-pass filter or calculation of the median of a spot image. Users can install their logics into the FPGA via VME bus. The IO daughter boards are simple IO modules such as analog inputs/outputs (AIOs) or digital inputs/outputs (DIOs). The data from the IO board is sent to the base board and processed there. As the IO daughter board is separated physically, the user can customize the VME board by choosing daughter boards and does not need to develop whole device. We have developed DIO, AIO, and Camera Link interface as the IO daughter board. In the presentation, design concept and implementation of this VME board are shown with some applications.  
WPPB14 Development of a Signal Processing Board for Spill Digital Servo System for Proton Synchrotron 430
 
  • T. Adachi, R. Muto, H. Sato, H. Someya, M. Tomizawa, H. Nakagawa
    KEK, Ibaraki
  • T. I. Ichikawa, K. Mochiki
    Musasi Institute of Technology, Instrumentation and Control Laboratory, Tokyo
  • A. Kiyomichi
    JAEA/J-PARC, Tokai-Mura, Naka-Gun, Ibaraki-Ken
  • K. Noda
    NIRS, Chiba-shi
  
  A prototype data processing board for a digital spill control system has been made. The system is considered to be used to control proton beams in 50-GeV synchrotron rings of J-PARC. The prototype circuit board consists of four ADCs, two FPGAs, a DSP, memories, and four DACs. The four inputs of the processing board are assumed to be an intensity signal of the proton beam in the accelerator rings, a digital gate signal that indicates the duration of beam extraction, a spill signal that shows the intensity of the extracted proton beam, and a reserved signal. The resolution and maximum sampling speed of the ADC are 16 bit and 2.5 Msps, respectively. One of the FPGAs is Vartex-2 1000-4C, and a real-time power spectrum analyzer will be implemented. It analyzes the spill signal every 1ms or shorter period. The analyzed result reflects optimum parameters used in spill control by servo. The DSP takes charge of these digital servo processing. The DACs with 16-bit resolution drive control signals for magnet currents. The system has another FPGA for communication between the processing board and network. MicroBlase CPU core is implemented, and uCLinux is installed to use EPICS.  
WPPB15 Beyond PCs: Accelerator Controls on Programmable Logic 433
 
  • J. Dedic, K. Zagar, M. Plesko
    Cosylab, Ljubljana
  
  The large number of gates in modern FPGAs including processor cores allows implementation of complex designs, including a core implementing Java byte-code as the instruction set. Instruments based on FPGA technology are composed only of digital parts and are totally configurable. Based on experience gained on our products (a delay generators producing sub-nanosecond signals and function generators producing arbitrary functions of length in the order of minutes) and on our research projects (a prototype hardware platform for real-time Java, where Java runtime is the operating system and there is no need for Linux), I will speculate about possible future scenarios: A combination of an FPGA processor core and custom logic will provide all control tasks, slow and hard real-time, while keeping our convenient development environment for software such as Eclipse. I will illustrate my claims with designs for tasks such as low-latency PID controllers running at several dozen MHz, sub-nanosecond resolution timing, motion control, and a versatile I/O controller–all implemented in real-time Java and on exactly the same hardware, just with different connectors.  
WPPB18 Customizable Motion Control Solution Supporting Large Distances 436
 
  • R. Baer, G. Froehlich, K. Herlo, U. Krause, M. Schwickert
    GSI, Darmstadt
  • J. Bobnar, I. Kriznar, J. Dedic
    Cosylab, Ljubljana
  
  Motion control solutions for controlling a movement of motorized mechanical subsystems for accelerators, telescopes or similar spatially distributed systems require high degree of flexibility regarding the use and connectivity. One platform should fit different applications and provide cost effective solutions. A connection to the control system (CS) is required on one side, while on the other side a connection to a variety of motors, position encoders and other feedback devices must be provided. In case of more complex mechanics, an advanced kinematics control is essential to provide features such as motion tuning, interpolation and controlled acceleration. An embedded computer is used for SW-flexibility and CS-support. Motion control capabilities are provided by separate HW; programmable multi axis controller. Signal adaptation for a direct connection of the equipment is managed by an interface board. Easy installation and debugging is provided by low-level local control; front panel switches and indicators, RS232 or direct keyboard and monitor access. An advanced approach is required in case of a larger distance between the motor controller and the motors with position encoders.  
WPPB20 Extended MicroIOC Family (LOCO) 439
 
  • D. Golob, R. Kovacic, M. Pelko, M. Plesko, A. Podborsek, M. Kobal
    Cosylab, Ljubljana
  
  MicroIOC is an affordable, compact, embedded computer designed for controlling and monitoring of devices via a control system (EPICS, ACS, and TANGO are supported). Devices can be connected to microIOC via Ethernet, serial, GPIB, other ports, or directly with digital or analog inputs and outputs, which makes microIOC a perfect candidate for a platform that integrates devices into your control system. Already over 90 microIOCs are installed in 18 labs over the world. LOgarithmic COnverter (LOCO) is a specialized microIOC used as a high-voltage power-supply distribution system for vacuum ion pumps. A single high-voltage power-supply controller can be used for delivering power to multiple ion pumps. A highly-accurate logarithmic-scale current measurement is provided on each pump, enabling an affordable and reliable pressure measurement ranging from 10-12 to 10-4 mbar.  
WPPB21 Integration of CANopen-Based Controllers with TINE Control System for PETRA 3 442
 
  • T. Delfs, S. W. Herb, B. Pawlowski, P. K. Bartkiewicz
    DESY, Hamburg
  
  For PETRA III, the high-brilliance third-generation light source being built now at DESY in Hamburg, Germany, we have established a new hardware development standard for controller designs. It includes communication on the fieldbus level, hardware interfacing to fieldbuses, and a communication application software layer for device firmware. The CAN bus and CANopen protocol were chosen as a primary fieldbus standard, and three branches of generic CANopen-compliant interfacing modules were designed for rapid controller hardware development. For fieldbus management, configuration, and integration with the TINE control system*, the generic TICOM (TINE-Based CANopen Manager) software was written. This document gives an overview of our fieldbus hardware development standard and of the key features of TICOM. It also describes the first applications built on top of the standard.

* http://tine.desy.de.

 
WPPB23 Metrological Testing of DLS Timing System 445
 
  • A. Gonias, M. T. Heron, Y. S. Chernousko
    Diamond, Oxfordshire
  • E. Pietarinen, J. Pietarinen
    MRF, Helsinki
  
  The Diamond timing system is the latest-generation development of the design, principles, and technologies currently implemented in the Advanced Photon Source and Swiss Light Source timing systems. It provides the ability to generate reference events, distribute them over a fiber-optic network, and decode and process them at the equipment to be controlled. The Diamond timing system has now been operational for over a year. The systematic characterization of the installed system, to understand the performance, and the results of these measurements are presented.  
WPPB24 High Dynamic Range Current Measurements with Machine Protection 448
 
  • D. A. Bartkoski, C. Deibele, C. Sibley, D. H. Thompson
    ORNL, Oak Ridge, Tennessee
  
  At the SNS a beam current measurement technique called CHuMPS (Chopper Machine Protection System) has been developed that is fast, has a large dynamic range, and is droop-free. Combined with the LEBT chopper controller, a beam in gap measurement is possible that can accurately measure the beam in the chopper gaps. The beam in gap measurement can then provide machine protection in the case of chopper failure. The same application can also measure waste beam from the ring injection stripper foil and provide fast protection from stripper foil failure.  
WPPB25 Realization of a Custom Designed FPGA Based Embedded Controller 451
 
  • M. Harvey, T. Hayes, L. T. Hoff, R. C. Lee, P. Oddo, K. Smith, F. Severino
    BNL, Upton, Long Island, New York
  
  As part of the low-level RF (LLRF) upgrade project at Brookhaven National Laboratory’s Collider-Accelerator Department (BNL C-AD), we have recently developed and tested a prototype high-performance embedded controller. This controller is a custom-designed PMC module employing a Xilinx V4FX60 FPGA with a PowerPC405 embedded processor and a wide variety of onboard peripherals (DDR2 SDRAM, FLASH, Ethernet, PCI, multi-gigabit serial transceivers, etc.). The controller is capable of running either an embedded version of LINUX or VxWorks, the standard operating system for RHIC front-end computers (FECs). We have successfully demonstrated functionality of this controller as a standard RHIC FEC and tested all onboard peripherals. We now have the ability to develop complex, custom digital controllers within the framework of the standard RHIC control system infrastructure. This paper will describe various aspects of this development effort, including the basic hardware, functional capabilities, development environment, kernel and system integration, and plans for further development.  
WPPB36 Ripple Diagnostic on BESSY II Power Supplies 466
 
  • T. Birke, T. Schneegans, I. Müller
    BESSY GmbH, Berlin
  
  Keeping the ripple of power-supply currents within the specification limits is crucial for the beam stability of the BESSY storage ring. Malfunctioning or aged electronic devices cause an increase of output ripple over the years. This increase is hardly noticed by the operator or operation analysis because the slow integrating AD converters for the current readbacks filter out the ripple. Furthermore, it is almost impossible to find the connection between certain beam movements or beam noise and the faulty power supply causing it. To improve this situation, ripple information for every power supply is required within the control system. The latest series of the CAN bus-connected power-supply interface cards used at BESSY provide an additional fast AD converter. With a sampling frequency of 83.5kHz, this ADC samples ripple information over one period of the mains voltage. The results are transferred over the CAN bus to the EPICS-based control system and can be processed in the usual ways. Using this setup, even temporarily increased ripple can be detected without complex measurement methods.  
WPPB37 Fast BPM DAQ System Using Windows Oscilloscope-based EPICS IOC 469
 
  • K. Furukawa, T. Suwada, M. Satoh
    KEK, Ibaraki
  • T. Kudou, S. Kusano
    MELCO SC, Tsukuba
  • J. W. Wang
    USTC, Hefei, Anhui
  
  The non-destructive beam position monitor (BPM) is an indispensable diagnostic tool for the stable beam operation. In the KEK linac, approximately nineteen BPMs with the strip-line type electrodes are used for the beam orbit measurement and orbit feedback. In addition, some of them are also used for the beam energy feedback loops. The current DAQ system consists of the digital oscilloscopes and the VME computers. They are connected with the GPIB, and a signal from each electrode is analyzed with a predetermined response function once per second by a VME computer that is connected to the upper-layer control servers via Ethernet. The KEKB injector linac is planned to be upgraded to perform the simultaneous injection for 4-rings. In this operation mode, a fast DAQ system is strongly required. In the current system, maximum DAQ rate is strictly limited by the oscilloscope performance, and it should be improved for the 50-Hz measurement. For these reasons, we made the decision to replace the current DAQ system with the fast digital oscilloscope. In this paper, we will present the system description of the new DAQ system, and the detailed result of the performance test will be presented.  
WPPB39 130-MHz, 16-Bit Four-Channel Digitizer 475
 
  • R. Akre, T. Straumann, K. D. Kotturi
    SLAC, Menlo Park, California
  
  The PAD (Phase and Amplitude Detector) was designed to digitize high-speed analog input data with large dynamic range. Because of its high speed and high resolution processing capability, it has been useful to applications beyond measuring phase and amplitude of RF signals and klystron beam voltages. These applications include beam-position monitors, bunch-length monitors, and beam-charge monitors. The digitizer used is the Linear Technologies LTC2208. It was the first 16-bit digitizer chip on the market capable of running at 119MHz; it is specified to run up to 130MHz. For each channel, the 16-bit digitized signal from the LTC2208 is clocked into a 64k sample FIFO. Commercial FIFOs are available that store up to 256k samples in the same package. The data are then read from the FIFO into the Arcturus Coldfire uCDIMM. A CPLD is used to handle triggering, resetting the FIFO, interfacing the Coldfire processor to the 4 FIFOs, and interrupting the Coldfire processor. The processor runs RTEMS version 4.7 and EPICS 3.14.8.2. There is an optional add-on available that attaches to the QSPI port on the PAD for reading 8 slow, 24-bit analog signals.  
WPPB40 LCLS Beam-Position Monitor Data Acquisition System 478
 
  • R. Akre, R. G. Johnson, K. D. Kotturi, P. Krejcik, E. Medvedko, J. Olsen, S. Smith, T. Straumann
    SLAC, Menlo Park, California
  
  In order to determine the transversal LCLS beam position from the signals induced by the beam in four stripline pickup electrodes, the BPM electronics have to process four concurrent short RF bursts with a dynamic range > 60dB. An analog front end conditions the signals for subsequent acquisition with a waveform digitizer and also provides a calibration tone that can be injected into the system in order to compensate for gain variations and drift. Timing of the calibration pulser and switches, as well as control of various programmable attenuators, is provided by an FPGA. Because no COTS waveform digitizer with the desired performance (>14bit, ≥119MSPS) was available, the PAD digitizer (see separate contribution WPPB39) was selected. It turned out that the combination of a waveform digitizer with a low-end embedded CPU running a real-time OS (RTEMS) and control system (EPICS) is extremely flexible and could very easily be customized for our application. However, in order to meet the BPM real-time needs (readings in < 1ms), a second Ethernet interface was added to the PAD so that waveforms can be shipped, circumventing the ordinary TCP/IP stack on a dedicated link.  
FOAA02 Timing and LLRF System of Japanese XFEL to Realize Femto-Second Stability 706
 
  • T. Fukui, N. Hosoda, H. Maesaka, T. Ohshima, T. Shintake
    RIKEN, Hyogo
  • K. Imai, M. Kourogi
    OPtical Comb, Inc., Yokohama
  • M. K. Kitamura, K. Tamasaku, Y. Otake
    RIKEN Spring-8 Harima, Hyogo
  • M. Musya
    University of electro-communications, Tokyo
  • T. Ohata
    JASRI/SPring-8, Hyogo-ken
  
  At SPring-8, the construction of a 5712-MHz linac and undulators as a light source for XFEL is in progress. There are two parts of the linac in accordance with requirements of phase accuracy to realize a stable SASE generation. One is a crest acceleration part using a sinusoidal wave. The other is an off-crest part that corresponds to a bunch compressor giving an energy chirp to a beam bunch. To generate the stable SASE, the beam energy stability of 10-4 is required. To obtain this stability, the accuracy of sub-picoseconds is required in the crest part, and several ten femto-seconds are necessary in the off-crest part. The requirement in the crest part was achieved by rf control instruments based on an electronic circuit in the SCSS prototype accelerator. However, realizing the several ten femto-seconds accuracy is almost impossible by the present electronic circuit technology. Therefore, for overcoming this fact, we employed laser technology. In this paper, we describe a system based on IQ control technology to obtain sub-picoseconds accuracy and an optical signal distribution system using an optical comb generator that could realize several ten femto-seconds accuracy.  
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FOAA03 The CERN LHC Central Timing, a Vertical Slice 711
 
  • P. Alvarez, J. C. Bau, S. Deghaye, I. Kozsar, J. Serrano, J. H. Lewis
    CERN, Geneva
  
  The design of the LHC central timing system depends strongly on the requirements for a Collider-type machine. The accelerators in the LHC injector chain cycle in sequences, each accelerator providing beam to the next as the energy increases. This has led to a timing system in which time is divided into cycles of differing characteristics. The LHC timing requirements are completely different, there are no cycles, and machine events are linked to machine processes such as injection, ramping, squeezing, physics, etc. These processes are modelled as event tables that can be played independently; the system must also provide facilities to send asynchronous events for punctual equipment synchronization and a real-time channel to broadcast machine information such as the beam type and its energy. This paper describes the implementation of the LHC timing system and also gives details on the synchronization in the LHC injector chain that manufactures various beams for LHC.  
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FOAB01 Imaging System Integration at the SNS 714
 
  • W. Blokland, K. C. Goetz, T. A. Pelaia, T. J. Shea
    ORNL, Oak Ridge, Tennessee
  
  Over the past several years, a variety of imaging systems have been deployed at Oak Ridge National Laboratory's (ORNL's) Spallation Neutron Source (SNS). The systems have supported accelerator instrumentation, neutron beam measurement, target commissioning, and laser diagnostics. For each application, performance requirements drove the choice of camera technology, and this naturally led to a variety of interfaces. This paper will describe the experience gained during the integration and operation of these systems. Several challenges will be highlighted, including algorithms for quantitative measurements, correlation with other accelerator data, real-time video distribution, and storage of large data sets. Although heterogeneous systems must continue to be deployed to meet imaging needs, some common tools and technologies have been identified and are expected to enhance system integration efforts.  
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FOAB02 Digital Phase Control System for SSRF Linac 717
 
  • D. K. Liu, L. Y. Yu, C. X. Yin
    SINAP, Shanghai
  
  SSRF 150MeV linac includes two klystrons and two solid power amplifers, which drive two klystrons, respectively. The accelerating section is constant gradient accelerating structure, and its working frequency is 2998MHz, six times the storage ring RF frequency. In order to reach the requirement for the RF phase stability (±1 degree), the full digital phase control system, which includes RF front-end, AD, DA, and FPGA, is designed. FPGA, the key for phase control system, contains digital I/Q demoulator (phase detector), digital I/Q modulator (phase shifter), and control algorithms. Klystron forward signal is down converted to IF (12.5MHz), which is detected by ADC with 50MHz clock. Digital I/Q is generated by ADC sampling data and then sent to control algorithms in FPGA. After processed by control algorithms, digital I/Q is converted to IF by DAC (50MHz). IF signal from DAC output is up converted to RF and sent to solid RF power amplifer. With the aid of FPGA, the whole period of closed-loop is about 80ns, and delay of closed-loop is less than 600ns. The test results of digital phase control system are presented in this paper.  
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FOAB03 Ethernet Based Embedded IOC for FEL Control Systems 720
 
  • A. C. Grippo, K. Jordan, S. W. Moore, D. W. Sexton, J. Yan
    Jefferson Lab, Newport News, Virginia
  
  An Ethernet-based embedded Input Output Controller (IOC) has been developed as part of an upgrade to the control system for the Free Electron Laser Project at Jefferson Lab. Currently most of the FEL systems are controlled, configured, and monitored using a central VME bus-based configuration. These crate-based systems are limited in growth and usually interleave multiple systems. In order to accommodate incremental system growth and lower channel costs, we developed a standalone system, an Ethernet-based embedded controller called the Single Board IOC (SBIOC). The SBIOC is a module that integrates an Altera FPGA and the Arcturus uCdimm Coldfire 5282 Microcontroller daughter card into one module, which can be easily configured for different kinds of I/O devices. The microcontroller is a complete System-on-Module, including highly integrated functional blocks. A real-time operating system, RTEMS, is cross-compiled with EPICS, allowing us to download the RTEMS kernel, IOC device supports, and databases into the microcontroller. This embedded IOC system has the features of a low-cost IOC, free open source RTOS, plug-and-play-like ease of installation, and flexibility.  
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