Paper | Title | Page |
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TUY02 | Embedded Device Control | 58 |
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The embedded device controller network is seen as an open-source, two tier framework that allows device controllers to control distributed devices at a 5 kHz rate. This network provides timing and data transmission to support a network of 200 input devices to be read into 30 cell controllers, resolve 200x200 control matrices, send the new outputs to the controllers and settle in 200 usecs. It also supports identification of system conditions at a resolution of 2 usecs and a reaction to system conditions in under 20 μs. This paper discusses the plan for development, characterization, and deployment. | ||
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TUP001 | Generic VME Interface for Linux 2.6 Kernels | 77 |
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From the beginning of the ESRF both the machine and beamline control instrumentations were based on VME diskless crates equipped with Motorola CPU boards running OS-9. The TACO client-server architecture was used for distributed control. Several modernization steps were performed to migrate from OS-9 to Linux running either on the VME CPU, or on a remote industrial PC connected to the crate using a PCI/VME bus coupler. An initial implementation of a generic VME driver interface was developed for Linux 2.4 which allowed the same VME driver code to work on the different platforms. This work presents the complete re-writing of the above VME layer to fully conform to the abstract bus/device interface provided in Linux 2.6. The new subsystem clearly separates the rolls of VME hosts, controlling the target VME bus, and VME devices, using generic bus functionality exported by the hosts. This structure supports safe hot-plug operations in multi CPU systems and IRQ handling, among other features. The existing VME host drivers (SBS Bit3 bus coupler and Tundra Universe II chip) and VME device drivers (for ESRF, Compcontrol and ADAS cards) were successfully ported to this new structure. | ||
Poster | ||
TUP002 | Performance Tests of Digital Signal Processing for GSI Synchrotron BPMs | 79 |
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The Beam Position Monitoring System at GSI heavy ion synchrotrons consists of twelve stations. Each of the four BPM plates is connected to a Libera Hadron unit from I-Tech Company for digitization and position calculation. The raw data of one BPM sampled by 125 MS/s with 14 Bit ADCs are reduced to about 20 MB/s by the onboard FPGA, resulting in a bunch-by-bunch position readout. In addition, different timing signals with various requirements are used to verify the functionality of the FPGA algorithms. For a closed orbit measurement, the data of all twelve Liberas have to be read in parallel. For communication, the Xilinx Rocket IOs is used, that allows up to 1GBit/s data output. Over a dedicated network, the data are merged for further usage on a high performance PC. We describe the general architecture and present first performance tests. | ||
TUP003 | A Modular Control System Based on ACS for Present and Future ANKA Insertion Devices | 82 |
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At the 2.5 GeV synchrotron facility ANKA, Forschungszentrum Karlsruhe, Germany, the Insertion Device group pioneered the development of superconductive undulators and was the first worldwide to test them with beam. The actual control system for this SCU14 prototype is based on industrial standard software and was up to now not embedded to the communication layer of ANKA Control System (ACS) and not to the ANKA Supervisory Control and Data Acquisition (SCADA) control system, PVSSII. The paper describes the implementation of a modular control system structure, based on object oriented (OO) technologies, including all the devices of existent and future ANKA-IDs. As a second topic the hardware solution, based on Cosylabs MIOC, to interface undulator motion control of gaps and scrapers, main power supply, corrector power supplies, temperature control and Interlocks is described. The integration of the housekeeping functions, cooling, vacuum control and Interlocks to PVSSII and their communication with ACS are discussed. | ||
Poster | ||
TUP004 | Application of AS-Interface to a Small Angle Neutron Scattering Experiment | 85 |
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AS-Interface according to IEC 62026-2 is a simple low level field bus system that is well established in industrial automation. It is designed for the easy connection of simple sensors and actuators like switches or valves and can be seen as a low level complement to primary fieldbus systems like PROFIBUS or DeviceNet. Although it is a well established and proven industrial technology, it is rarely seen in research application. In order to simplify cabling and improve overall diagnostics, Forschungszentrum Jülich introduced AS-Interface into the control system of the small angle neutron scattering experiment KWS1. The paper gives an overview of the AS-I technology. The control system of KWS1 and experiences with AS-I are presented. | ||
Slides | ||
Poster | ||
TUP005 | Overview of the Personnel Safety System at the Heidelberg Ion Therapy Facility | 88 |
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The HIT (Heidelberg Ion Beam Therapy) Centre is the first heavy ion therapy accelerator in Europe, which is operated by the university hospital of Heidelberg, Germany. In accordance with the german radiological protection ordinance, a personnel safety system (PSS) was installed during the comissioning of the accelerator. Main functions of the PSS are radiation protection, gate control, emergency stop handling, change of the state of the protection areas and safety interlocks. The PSS is a stand alone part of the accelerator control system and consists of several OPC servers and a special designed GUI for the control room. The installation of the PSS was started in June 2006 and finished in March 2008. This presentation will report on the concept and realization of the PSS. | ||
TUP006 | Improved Function Generator for Device Control for the GSI Control System | 91 |
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In the GSI control system a function generator (FG) is used to control equipment with timing functions (ramps). It is situated between the real-time equipment controller (EC) and the actual device control electronics. It provides a 24 bit wide output with an internal accuracy of 32 bits. In ramping mode the FG is configured from the EC with interpolation points. By interpolating the function values the communication on the field bus is minimized. Presently, the interpolation in the FG is linear, which requires only one accumulator of 32 bit width. To better fit the physical functions with less interpolation points we have extended the generator to quadratic interpolation implementing a 2-dimensional arithmetic progression algorithm. This is realized with a datapath of two accumulators. The system should be able to use the complete dynamic range of 215 bits (signed) within one interpolating interval. To meet these requirements the input has to be shifted and the internal accuracy of the datapath has to be 40 bits. Simulations of the datapath have shown that although the accumulators uses more resources, the system performance requires only a low cost FPGA like the Altera CycloneII. | ||
TUP007 | Machine-Mode Aware Beam Loss Monitoring | 93 |
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Beam-loss level monitoring is a powerful diagnostic tool concerning accelerator health. Particles leave the vacuum pipe for various reasons, such as intrabeam scattering (Touschek effect), residual gas molecules, closed orbit distortions or mechanical obstacles (aperture restrictions, installation errors). These can be identified by appropriate measurements. The steady-state beam loss level varies throughout the machine and has to be measured and documented for further reference. Besides general radiation safety purposes, changes (especially increases) occurring after machine upgrades are of special interest. When simple monitoring of average beam loss fluctuations is insufficient, problem diagnostics should be further enhanced by correlating beam loss monitor (BLM) detector readout with events in the machine. For best flexibility, pulses should only be counted at certain conditions and during well defined time slots synchronized with the current machine operation cycle. In cooperation with Cosylab, such an advanced BLM acquisition system was developed for the Electron Stretcher Accelerator ELSA (University of Bonn, Germany), allowing various optimized acquisition modes. | ||
Poster | ||
WEZ01 | The TINE Common Device Interface in Operation | 154 |
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The Common Device Interface (CDI)* is the primary device layer used in the TINE** control system. It offers a generic, database-driven view of a servers hardware, where a hardware address, irrespective of the underlying bus, simply appears as a named device, which is accessed via the TINE client API. To date, CDI-supported busses include several CAN implementations, RS232, TwinCat***, Libera****, Siemens PLC, as well as the DESY in-house bus SEDAC. In this paper, we report on the latest features of CDI and more importantly on the first experiences of using CDI in operations, primarily in the PETRA3 pre-accelerator chain and in DC, Servo, and stepper motor control at the EMBL beamlines.
* Duval and Wu, Using the Common Device Interface in TINE, Proceedings PCaPAC 2006. ** http://tine.desy.de *** http://www.beckhoffautomation.com **** http://www.i-tech.si/products.php |
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WEZ02 | The Canadian Light Source Control System - A Case Study in the Use of Single Board Computers and Industrial PC Equipment for Synchrotron Control | 157 |
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Since 2000 the Canadian Light Source (CLS) control system architecture has been based on to the use of small single board computers for equipment control running the RTEMS operating system. CLS has started to migrate to a new off-the-shelf single board computer platform (based on the Moxa embedded computer platform. In 2001 CLS also adopted the use of fibre optic bridges and industrial PC equipment in place of VME slot zero controllers. Today this continues to be the basis of our higher performance data acquisition and control applications. This paper outlines the lessons learned from nearly eight years of operational use of the this technology. | ||
Slides | ||
WEZ03 | A configurable Interlock System for RF Stations at XFEL | 159 |
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The interlock system prevents any damage from the cost expensive components of the RF station. The system monitors various system components, computes the status in-formation in realtime and reports actual status to the control system. The system is designed for maximum reliability and max. time of operation. It includes self diagnostic and modular repair strategies. The interlock incorporates a controller and slave modules that perform the I/O opera-tion. They are connected to distribution panels that supply flexible interfaces to exter-nal components. The interlock logic is implemented in hardware and operates independ from the proc-essor and the software. The software accomplishes the hardware selftest on system startup. Further applications provide communication interfaces over Ethernet used by administration and the controlsystem. A runtime software integrity selftest strategy has been implemented for high reliability. It covers detection of stack overflows, thread deadlocks, memory corruption and is able to recover the system without inter-rupting interlock operation. The interlock system performs well its task at FLASH (DESY, Hamburg Site) and at PITZ (DESY, Zeuthen Site). | ||
Slides | ||
WEZ04 | Using the Advanced Telecom Computing Architecture xTCA as Crate Standard for XFEL | 162 |
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At XFEL it is planned to install most electronic components and computers for LLRF, diagnostics and controls inside the tunnel. Access to these devices during the XFEL operation will not be possible. Remote control and monitoring of all relevant parameters of the shelfs/crates and the computers must be ensured and should be done in a standardised way. In addition software downloads and debugging up to the FPGA level should be provided, even if an operating system crashes e.g. due to radiation, maintenance functionality must be available. An introduction to xTCA will be given, the reasons to change the crate standard from a VME to a xTCA based system and the experience with this new electronics standard will be described. | ||
Slides |