Keyword: FPGA
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TUPLR047 Commissioning of XBox-3: A Very High Capacity X-band Test Stand klystron, LLRF, controls, detector 568
 
  • N. Catalán Lasheras, C.F. Eymin, J. Giner Navarro, G. McMonagle, S.F. Rey, A. Solodko, I. Syratchev, B.J. Woolley, W. Wuensch
    CERN, Geneva, Switzerland
  • T. Argyropoulos, D. Esperante Pereira
    IFIC, Valencia, Spain
  • M. Volpi
    The University of Melbourne, Melbourne, Victoria, Australia
 
  The Compact Linear Collider (CLIC) beam-based acceleration baseline uses high-gradient travelling wave accelerating structures at a frequency of 12 GHz. In order to prove the performance of these structures at high peak power and short pulse width RF, two klystron-based test facilities have been put in operation in the last years. The third X-band testing facility at CERN (Xbox3) has recently been commissioned and has tripled the number of testing slots available. Xbox3 uses a novel way of combining relatively low peak power (6 MW) but high average power klystron units whose power is steered to feed four testing slots with RF to the required power with a repetition rate of up to 400 Hz. Besides the repetition rate, peak power, pulse length and pulse shape can be customized to fit the test requirements. This novel way of combining pulsed RF high power can eventually be used for many other applications where multiple test slots are required.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-LINAC2016-TUPLR047  
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THPLR038 Resonance Control for Narrow Bandwidth PIP-II Cavities cavity, resonance, flattop, SRF 936
 
  • W. Schappert, J.P. Holzbauer, Y.M. Pischalnikov
    Fermilab, Batavia, Illinois, USA
 
  The PIP-II project at FNAL calls for a SRF pulsed proton driver linac to support the expanding neutrino physics program including DUNE/LBNF. The relatively low beam current and high quality factors called for in the design means that these cavities will be operated with small RF bandwidths, meaning that they will be sensitive to microphonics. Combined with a 20 Hz pulsed operational structure and the use of four different, complex cavity geometries means that resonance control will be extremely challenging. Work is ongoing at FNAL to develop active resonance stabilization techniques using fast piezoelectric tuners in support of PIP-II. These techniques as well as testing and development results using a prototype, dressed low-beta single-spoke cavity will be presented along with an outlook for future efforts.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-LINAC2016-THPLR038  
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THPLR043 EPICS IOC Prototype of FRIB Machine Protection System status, interface, controls, hardware 949
 
  • L. Wang, M. Ikegami, Z. Li, G. Shen, S. Zhao
    FRIB, East Lansing, USA
  • M.A. Davis
    NSCL, East Lansing, Michigan, USA
 
  Funding: Work supported by the U.S. Department of Energy Office of Science under Cooperative Agreement DE-SC0000661
The FRIB Machine Protection System (MPS) is designed to protect accelerator components from damage by the beam in case of operating failure. MPS includes master and slave nodes, which are controlled by MPS IOC. In this paper, we present design of MPS IOC and status of its prototyping.
 
poster icon Poster THPLR043 [0.500 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-LINAC2016-THPLR043  
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THPLR046 FRIB Fast Machine Protection System: Engineering for Distributed Fault Monitoring System and Light Speed Response status, network, timing, linac 959
 
  • Z. Li, L.R. Dalesio, M. Ikegami, S.M. Lidia, L. Wang, S. Zhao
    FRIB, East Lansing, USA
 
  Funding: Work supported by the U.S. Department of Energy Office of Science under Cooperative Agreement DE-SC0000661
The Facility for Rare Isotope Beams (FRIB), a high-power, heavy ion facility, can accelerate beam up to 400 kW power with kinetic energy ≥ 200 MeV/u. Its fast protection system is required to detect failure and remove beam within 35 μs to prevent damage to equipment. The fast protection system collects OK/NOK inputs from hundreds of devices, such as low level RF controllers, beam loss monitors, and beam current monitors, which are distributed over 200 m. The engineering challenge here is to design a distributed control system to collect status from these devices and send out the mitigation signals within 10 μS timing budget and also rearm for the next pulse for 100 Hz beam (10 mS). This paper describes an engineering solution with a master-slave structure adopted in FRIB. Details will be covered from system architecture to FPGA hardware platform design and from communication protocols to physical interface definition. The response time of ~9.6μS from OK/NOK inputs to mitigation outputs is reached when query method is used to poll the status. A new approach is outlined to use bi-direction loop structure for the slave chain and use streaming mode for data collection from slave to master, ~3μS response time are expected from this engineering optimization.
 
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DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-LINAC2016-THPLR046  
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THPLR048 Development of a Digital LLRF Control System at LNL controls, cavity, LLRF, radio-frequency 966
 
  • S. Pavinato, M. Betti, D. Bortolato, F. Gelain, D. Marcato, D. Pedretti
    INFN/LNL, Legnaro (PD), Italy
  • M.A. Bellato, R. Isocrate
    INFN- Sez. di Padova, Padova, Italy
  • M. Bertocco
    UNIPD, Padova (PD), Italy
 
  The new Low-Level Radio Frequency (LLRF) control system for linear accelerator at Legnaro National Laboratories (LNL) of INFN is presently being commissioned. A digital Radio Frequency (RF) controller was implemented. Its goal is to stabilize the amplitude, the phase and the frequency of the superconducting cavities of the Linac. The resonance frequency of the low beta cavities is 80 MHz, while medium and high beta cavities resonate at 160 MHz. Each RF controller controls at the same time eight different cavities. The hardware complexity of the RF controller (RF IOC) is reduced by adopting direct RF sampling and the RF to baseband conversion method. The main hardware components are RF ADCs for the direct undersampling of the signals picked up from cavities, a Xilinx Kintek 7 FPGA for the signal processing and DACs for driving the power amplifiers and hence the cavities. In the RF IOC the serial communication between FPGA and ADCs and between FPGA and DACs is based on JESD204b standard. An RF front-end board (RFFE) is placed between cavities and the RF IOC. This is used to adapt the power level of the RF signal from the cavities to the ADCs and from the DACs to the power amplifiers. This paper addresses the LLRF control system focusing on the hardware design of the RF IOC and RFFE boards and on the first test results carried out with the new controller.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-LINAC2016-THPLR048  
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