Diversified Technologies, Inc., Bedford, Massachusetts, USA
Semiconductor thyristors have long been used as a replacement for thyratrons in low power or long pulse RF systems. To date, however, such thyristor assemblies have not demonstrated the reliability needed for installation in short pulse, high peak power RF stations used with many pulsed electron accelerators. The fast rising current in a thyristor tends to be carried in a small region, rather than across the whole device, and this localized current concentration can cause a short circuit failure. An alternate solid-state device, the insulated-gate bipolar transistor (IGBT), can readily operate at the speed needed for the accelerator, but commercial IGBTs cannot handle the voltage and current required. It is, however, possible to assemble these devices in arrays to reach the required performance levels without sacrificing their inherent speed. Diversified Technologies, Inc. (DTI) has patented and refined the technology required to build these arrays of series-parallel connected switches. DTI is currently developing an affordable, reliable, form-fit-function replacement for the klystron modulator thyratrons at SLAC capable of pulsing at 360 kV, 420 A, 6μs, and 120 Hz.
FRIB, East Lansing, USA
The Facility for Rare Isotope Beams (FRIB), a high-power, heavy ion facility, can accelerate beam up to 400 kW power with kinetic energy ≥ 200 MeV/u. Its fast protection system is required to detect failure and remove beam within 35 μs to prevent damage to equipment. The fast protection system collects OK/NOK inputs from hundreds of devices, such as low level RF controllers, beam loss monitors, and beam current monitors, which are distributed over 200 m. The engineering challenge here is to design a distributed control system to collect status from these devices and send out the mitigation signals within 10 μS timing budget and also rearm for the next pulse for 100 Hz beam (10 mS). This paper describes an engineering solution with a master-slave structure adopted in FRIB. Details will be covered from system architecture to FPGA hardware platform design and from communication protocols to physical interface definition. The response time of ~9.6μS from OK/NOK inputs to mitigation outputs is reached when query method is used to poll the status. A new approach is outlined to use bi-direction loop structure for the slave chain and use streaming mode for data collection from slave to master, ~3μS response time are expected from this engineering optimization.
