| Paper | Title | Page |
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| WPPB01 | CTF3 Beam Position Monitor Acquisition System | 395 |
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| The CLIC Test Facility 3 (CTF3) is an R&D machine being built to validate concepts that will be used for the Compact Linear Collider (CLIC). Because CTF3 is an instrumentation-intensive machine, a considerable amount of money is put into the acquisition hardware and high-quality cables used to bring the instrument signals to the digitalization crates with as little degradation as possible. The main idea of this new approach is to reduce the distance between the signal source and the A/D conversion, reducing the cost of the cabling. To achieve that, we have developed a radiation hard front-end that we install directly into the accelerator tunnel. This front-end deals with the digitalization of the signals after an analog buffering. Afterwards, the data are sent to a computer through the SPECS field bus. Finally, the digitalized signals are made available to the operation crew thanks to a server implementing the OASIS (Open Analogue Signal Information System) interfaces in the CERN Front-End Software Architecture (FESA). After a presentation of this low-cost solution to BPM acquisition, the paper gives the results of the first integration tests performed in the CTF3 machine. | ||
| WPPB02 | The LHC Central Timing Hardware Implementation | 400 |
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| The LHC central timing requirements are very different from those of the injector chain. Not only is machine's safety and reliability critical, but there are other important differences that have forced a new approach. Unlike the injector chain, the LHC processes cannot be usefully broken up into basic time periods and cycles; rather, they are independent, asynchronous, and of arbitrary duration. This paper presents the hardware and low-level software solutions we adopted and the technologies we used to implement them—in particular, the use of reflective memory, reliable use of the global positioning system as a precise time reference, redundancy, transmission-time calibration, safe beam parameter distribution, and the multitasking event generation hardware we developed to control the LHC machine processes. | ||
| WPPB03 | Software Interlocks System | 403 |
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| In the year 2006, a first operational version of a new Java-based Software Interlock System (SIS) was introduced to protect parts of the SPS (Super Proton Synchrotron) complex, mainly CNGS (CERN Neutrinos to Gran Sasso), TI8 (SPS transfer line), and for some areas of the SPS ring. SIS protects the machine through surveillance and by analyzing the state of various key devices and dumping or inhibiting the beam if a potentially dangerous situation occurs. Being a part of the machine protection, it shall gradually replace the old SPS Software Interlock System (SSIS) and reach the final operational state targeting LHC (Large Hadron Collider) in 2008. The system, which was designed with the use of modern, state-of-the-art technologies, proved to be highly successful and very reliable from the very beginning of its existence. Its relatively simple and very open architecture allows for fast and easy configuration and extension to meet the demanding requirements of the forthcoming LHC era. | ||
| WPPB04 | Convergence Computer–Communication Methods for Advanced High-Performance Control System | 406 |
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| Based on analysis of advanced computer and communication system architectures, a future control system approach is proposed and discussed in this paper. Convergence computer and communication technologies are moving to high-performance modular system architectures on the basis of high-speed switched interconnections. Multicore processors become more perspective ways to high-performance systems, and traditional parallel bus system architectures are extended by higher-speed serial switched interconnections. Compact modular system on the base of passive 3-4 slots PCI bas with fast switch network interconnection are described as examples of a modern, scalable control system solution, which can be compatible extended to advanced system architecture on the basis of new technologies (ATCA,μTCA). Kombi wired and wireless subnets can be used as effective platforms also for large experimental physics control systems and complex computer automation in an experimental area with human interactions inside systems by IP-phones. | ||
| WPPB06 | Synchronization System of Synchrotron SOLEIL | 409 |
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| To bring electrons from the LINAC to the storage ring, much equipment must be triggered synchronously to the beam. The timing system provides the time base needed for this purpose. More than a simple clocks distribution system, it is a real network, broadcasting clocks and data all over the synchrotron. Data are used to send events to equipment: for example, injection of electrons inside the booster, extraction of electrons from the booster to the storage ring, or even triggering diagnostic equipment. The timing system is made up of a standalone CENTRAL system and several cPCI LOCAL boards. The CENTRAL system provides clocks and data and broadcasts them to the LOCAL boards through an optical fiber network. LOCAL boards are placed close to the equipment, and they provide delayed signals to trigger them. These delays can be precisely adjusted by the user, making the equipment synchronous with the electron beam. After a brief explanation of our needs, the presentation describes the timing systems (architecture, performance, etc.) used at SOLEIL. It also describes the results after a year of use: the good, the bad, and the truth (well, maybe). | ||
| WPPB07 | Machine Protection and Advanced Plasma Control in TORE SUPRA Tokamak | 412 |
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| A tokamak is a complex device combining many sub-systems. All of them must have high reliability and robustness to operate together. A sub-system includes its own safety protections and a more integrated level of protection to ensure the safety of the full device. Moreover, plasma operation with several megawatts of additional injected power requires a highly reliable and performing control because uncontrolled plasma displacements and off-normal events could seriously damage the in-vessel components. Such an integrated control system is installed on Tore Supra. It can develop an alternative plasma operation strategy when margins to technological sub-system limits become too small. The control switches to more and more degraded modes, from the nominal one to a fast plasma shutdown. When sub-system limits are nearly reached, the system tries to balance the loads over less solicited parts. Then a modification of the plasma parameters is performed to preserve the plasma discharge in a degraded mode. The third step is a soft and controlled plasma shutdown, including a stopping of additional heating systems. When loads are closed to be uncontrolled, a fast plasma shutdown is initiated. | ||
| WPPB08 | Role-Based Authorization in Equipment Access at CERN | 415 |
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| Given the significant dangers of LHC operations, Role-Based Access Control (RBAC) is designed to protect from accidental and unauthorized access to the LHC and injector equipment. Role-Based Authorization is part of this approach. It has been implemented in the Controls Middleware (CMW) infrastructure so that access to equipment can be restricted according to Access Rules defined jointly by the equipment and operation groups. This paper describes the authorization mechanism, the definition and management of Access Rules and the implementation of this mechanism within the CMW. | ||
| WPPB10 | Virtually There: The Control Room of the Future | 418 |
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Imagine the ILC is up and running. Electrons and positrons collide happily, and scientists are taking data. Suddenly there's a problem with one of the laser wires. All experts are at a meeting on a different continent, but the problem needs to be fixed immediately. Difficult? Not when there's a Global Accelerator Network Multipurpose Virtual Lab (GANMVL) in place. High-speed, high-resolution cameras would allow the faraway experts to look at the fault, a web-based portal would let them access the controls and tools of the system with a simple "single-sign-on" procedure. However, the virtual lab is not just about remote operation. In principle it is already possible to run a control room remotely. This system is radically different in that it takes into account the human aspect of teamwork around the world. The implications of a working virtual control room are enormous. It might revolutionise virtual collaboration in completely different areas. The paper presents the GANMVL tool and the results of the evaluation of the Virtual Lab in production environment and real operations.
* http://www.eurotev.org/, “European Design Study Towards a Global TeV Linear Collider.” ** http://www.linearcollider.org/cms/, “International linear collider.” |
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| WPPB11 | Secure Remote Operations of NSLS Beamlines with (Free)NX | 421 |
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| In light source beamlines, there are times when remote operations from users are desired. This becomes challenging, considering cybersecurity has been dramatically tightened throughout many facilities. Remote X-windows display to Unix/Linux workstations at the facilities, either with straight x-traffic or tunneling through ssh (ssh -XC), is quite slow over long distance, thus not quite suitable for remote control/operations. We implemented a solution that employs the open source FreeNX technology. With its efficient compression technology, the bandwidth usage is quite small and the response time from long distance is very impressive. The setup we have, involves a freenx server configured on the linux workstation at the facility and free downloadable clients (Windows, Mac, Linux) at the remote site to connect to the freenx servers. All traffic are tunneled through ssh, and special keys can be used to further security. The response time is so good that remote operations are routinely performed. We believe this technology can have great implications for other facilities, including those for the high energy physics community. | ||
| WPPB12 | High-Speed X-ray Imaging at NSLS | 424 |
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| We describe two projects currently underway at National Synchrotron Light Source (NSLS). The first is an inexpensive yet high-performance image acquisition system utilizing a low-cost firewire camera, a PMC firewire interface board, EPICS and the in-house written RTEMS-mvme5500 Board Support Package. The BSP, EPICS/RTEMS software and firewire drivers demonstrate a high throughput of image display for the 1024x768x8bit mode of 30 frames per second (fps) of data transfer, while triggering EPICS display at 30 Hz simultaneously. The second is the readout system for the LCLS X-ray Active Matrix Pixel Sensor (XAMPS) detector. The specification of the detector readout requires a 1024x1024x14bit image to be stored to disk at 120 Hz, an average data rate of 252 Mega Bytes/sec. A faster SBC was chosen to be interfaced with a FPGA based PMC card and Fiber Channel storage system. This cost-effective prototype will function efficiently and reliably as a data acquisition system for the implementation of the XAMPS detector developed at the NSLS. Modern software and the use of commercial hardware technology has cut our cost of both systems, and delivered excellent performance. | ||
| WPPB13 | Development of Flexible and Logic-Reconfigurable VME Boards | 427 |
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| We developed a logic-reconfigurable VME board with high flexibility. The board has two parts, a base board and two IO daughter boards. The base board has a field programmable gate arrays (FPGA) chip for execution of user logic, such as a digital low-pass filter or calculation of the median of a spot image. Users can install their logics into the FPGA via VME bus. The IO daughter boards are simple IO modules such as analog inputs/outputs (AIOs) or digital inputs/outputs (DIOs). The data from the IO board is sent to the base board and processed there. As the IO daughter board is separated physically, the user can customize the VME board by choosing daughter boards and does not need to develop whole device. We have developed DIO, AIO, and Camera Link interface as the IO daughter board. In the presentation, design concept and implementation of this VME board are shown with some applications. | ||
| WPPB14 | Development of a Signal Processing Board for Spill Digital Servo System for Proton Synchrotron | 430 |
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| A prototype data processing board for a digital spill control system has been made. The system is considered to be used to control proton beams in 50-GeV synchrotron rings of J-PARC. The prototype circuit board consists of four ADCs, two FPGAs, a DSP, memories, and four DACs. The four inputs of the processing board are assumed to be an intensity signal of the proton beam in the accelerator rings, a digital gate signal that indicates the duration of beam extraction, a spill signal that shows the intensity of the extracted proton beam, and a reserved signal. The resolution and maximum sampling speed of the ADC are 16 bit and 2.5 Msps, respectively. One of the FPGAs is Vartex-2 1000-4C, and a real-time power spectrum analyzer will be implemented. It analyzes the spill signal every 1ms or shorter period. The analyzed result reflects optimum parameters used in spill control by servo. The DSP takes charge of these digital servo processing. The DACs with 16-bit resolution drive control signals for magnet currents. The system has another FPGA for communication between the processing board and network. MicroBlase CPU core is implemented, and uCLinux is installed to use EPICS. | ||
| WPPB15 | Beyond PCs: Accelerator Controls on Programmable Logic | 433 |
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| The large number of gates in modern FPGAs including processor cores allows implementation of complex designs, including a core implementing Java byte-code as the instruction set. Instruments based on FPGA technology are composed only of digital parts and are totally configurable. Based on experience gained on our products (a delay generators producing sub-nanosecond signals and function generators producing arbitrary functions of length in the order of minutes) and on our research projects (a prototype hardware platform for real-time Java, where Java runtime is the operating system and there is no need for Linux), I will speculate about possible future scenarios: A combination of an FPGA processor core and custom logic will provide all control tasks, slow and hard real-time, while keeping our convenient development environment for software such as Eclipse. I will illustrate my claims with designs for tasks such as low-latency PID controllers running at several dozen MHz, sub-nanosecond resolution timing, motion control, and a versatile I/O controller–all implemented in real-time Java and on exactly the same hardware, just with different connectors. | ||
| WPPB18 | Customizable Motion Control Solution Supporting Large Distances | 436 |
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| Motion control solutions for controlling a movement of motorized mechanical subsystems for accelerators, telescopes or similar spatially distributed systems require high degree of flexibility regarding the use and connectivity. One platform should fit different applications and provide cost effective solutions. A connection to the control system (CS) is required on one side, while on the other side a connection to a variety of motors, position encoders and other feedback devices must be provided. In case of more complex mechanics, an advanced kinematics control is essential to provide features such as motion tuning, interpolation and controlled acceleration. An embedded computer is used for SW-flexibility and CS-support. Motion control capabilities are provided by separate HW; programmable multi axis controller. Signal adaptation for a direct connection of the equipment is managed by an interface board. Easy installation and debugging is provided by low-level local control; front panel switches and indicators, RS232 or direct keyboard and monitor access. An advanced approach is required in case of a larger distance between the motor controller and the motors with position encoders. | ||
| WPPB20 | Extended MicroIOC Family (LOCO) | 439 |
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| MicroIOC is an affordable, compact, embedded computer designed for controlling and monitoring of devices via a control system (EPICS, ACS, and TANGO are supported). Devices can be connected to microIOC via Ethernet, serial, GPIB, other ports, or directly with digital or analog inputs and outputs, which makes microIOC a perfect candidate for a platform that integrates devices into your control system. Already over 90 microIOCs are installed in 18 labs over the world. LOgarithmic COnverter (LOCO) is a specialized microIOC used as a high-voltage power-supply distribution system for vacuum ion pumps. A single high-voltage power-supply controller can be used for delivering power to multiple ion pumps. A highly-accurate logarithmic-scale current measurement is provided on each pump, enabling an affordable and reliable pressure measurement ranging from 10-12 to 10-4 mbar. | ||
| WPPB21 | Integration of CANopen-Based Controllers with TINE Control System for PETRA 3 | 442 |
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For PETRA III, the high-brilliance third-generation light source being built now at DESY in Hamburg, Germany, we have established a new hardware development standard for controller designs. It includes communication on the fieldbus level, hardware interfacing to fieldbuses, and a communication application software layer for device firmware. The CAN bus and CANopen protocol were chosen as a primary fieldbus standard, and three branches of generic CANopen-compliant interfacing modules were designed for rapid controller hardware development. For fieldbus management, configuration, and integration with the TINE control system*, the generic TICOM (TINE-Based CANopen Manager) software was written. This document gives an overview of our fieldbus hardware development standard and of the key features of TICOM. It also describes the first applications built on top of the standard.
* http://tine.desy.de. |
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| WPPB23 | Metrological Testing of DLS Timing System | 445 |
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| The Diamond timing system is the latest-generation development of the design, principles, and technologies currently implemented in the Advanced Photon Source and Swiss Light Source timing systems. It provides the ability to generate reference events, distribute them over a fiber-optic network, and decode and process them at the equipment to be controlled. The Diamond timing system has now been operational for over a year. The systematic characterization of the installed system, to understand the performance, and the results of these measurements are presented. | ||
| WPPB24 | High Dynamic Range Current Measurements with Machine Protection | 448 |
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| At the SNS a beam current measurement technique called CHuMPS (Chopper Machine Protection System) has been developed that is fast, has a large dynamic range, and is droop-free. Combined with the LEBT chopper controller, a beam in gap measurement is possible that can accurately measure the beam in the chopper gaps. The beam in gap measurement can then provide machine protection in the case of chopper failure. The same application can also measure waste beam from the ring injection stripper foil and provide fast protection from stripper foil failure. | ||
| WPPB25 | Realization of a Custom Designed FPGA Based Embedded Controller | 451 |
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| As part of the low-level RF (LLRF) upgrade project at Brookhaven National Laboratory’s Collider-Accelerator Department (BNL C-AD), we have recently developed and tested a prototype high-performance embedded controller. This controller is a custom-designed PMC module employing a Xilinx V4FX60 FPGA with a PowerPC405 embedded processor and a wide variety of onboard peripherals (DDR2 SDRAM, FLASH, Ethernet, PCI, multi-gigabit serial transceivers, etc.). The controller is capable of running either an embedded version of LINUX or VxWorks, the standard operating system for RHIC front-end computers (FECs). We have successfully demonstrated functionality of this controller as a standard RHIC FEC and tested all onboard peripherals. We now have the ability to develop complex, custom digital controllers within the framework of the standard RHIC control system infrastructure. This paper will describe various aspects of this development effort, including the basic hardware, functional capabilities, development environment, kernel and system integration, and plans for further development. | ||
| WPPB28 | Remote Operation of Large-Scale Fusion Experiments | 454 |
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| This paper examines the past, present, and future remote operation of large-scale fusion experiments by large, geographically dispersed teams. The fusion community has considerable experience placing remote collaboration tools in the hands of real users. Tools to remotely view operations and control selected instrumentation and analysis tasks were in use as early as 1992 and full remote operation of an entire tokamak experiment was demonstrated in 1996. Today’s experiments invariable involve a mix of local and remote researchers, with sessions routinely led from remote institutions. Currently, the National Fusion Collaboratory Project has created a FusionGrid for secure remote computations and has placed collaborative tools into operating control rooms. Looking toward the future, ITER will be the next major step in the international program. Fusion experiments put a premium on near real-time interactions with data and among members of the team and though ITER will generate more data than current experiments, the greatest challenge will be the provisioning of systems for analyzing, visualizing and assimilating data to support distributed decision making during ITER operation. | ||
| WPPB30 | Cybersecurity and User Accountability in the C-AD Control System | 457 |
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| A heightened awareness of cybersecurity has led to a review of the procedures that ensure user accountability for actions performed on the computers of the Collider-Accelerator Department (C-AD)Control System. Control system consoles are shared by multiple users in control rooms throughout the C-AD complex. A significant challenge has been the establishment of procedures that securely control and monitor access to these shared consoles without impeding accelerator operations. This paper provides an overview of C-AD cybersecurity strategies with an emphasis on recent enhancements in user authentication and tracking methods. | ||
| WPPB32 | Cybersecurity in ALICE DCS | 460 |
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| In the design of the control system for the ALICE experiment much emphasis has been put on cyber security. The control system operates on a dedicated network isolated from the campus network and remote access is only granted via a set of Windows Server 2003 machines configured as application gateways. The operator consoles are also separated from the control system by means of a cluster of terminal servers. Computer virtualization techniques are deployed to grant time-restricted access for sensitive tasks such as control system modifications. This paper will describe the global access control architecture and the policy and operational rules defined. The role-based authorization schema will also be described as well as the tools implemented to achieve this task. The authentication based on smartcard certificates will also be discussed. | ||
| WPPB34 | Information Technology Security at the Advanced Photon Source | 463 |
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| The proliferation of “bot” nets, phishing schemes, denial-of-service attacks, root kits, and other cyber attack schemes designed to capture a system or network creates a climate of worry for system administrators, especially for those managing accelerator and large experimental-physics facilities as they are very public targets. This paper will describe the steps being taken at the Advanced Photon Source (APS) to protect the infrastructure of the overall network with emphasis on security for the APS control system. | ||
| WPPB36 | Ripple Diagnostic on BESSY II Power Supplies | 466 |
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| Keeping the ripple of power-supply currents within the specification limits is crucial for the beam stability of the BESSY storage ring. Malfunctioning or aged electronic devices cause an increase of output ripple over the years. This increase is hardly noticed by the operator or operation analysis because the slow integrating AD converters for the current readbacks filter out the ripple. Furthermore, it is almost impossible to find the connection between certain beam movements or beam noise and the faulty power supply causing it. To improve this situation, ripple information for every power supply is required within the control system. The latest series of the CAN bus-connected power-supply interface cards used at BESSY provide an additional fast AD converter. With a sampling frequency of 83.5kHz, this ADC samples ripple information over one period of the mains voltage. The results are transferred over the CAN bus to the EPICS-based control system and can be processed in the usual ways. Using this setup, even temporarily increased ripple can be detected without complex measurement methods. | ||
| WPPB37 | Fast BPM DAQ System Using Windows Oscilloscope-based EPICS IOC | 469 |
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| The non-destructive beam position monitor (BPM) is an indispensable diagnostic tool for the stable beam operation. In the KEK linac, approximately nineteen BPMs with the strip-line type electrodes are used for the beam orbit measurement and orbit feedback. In addition, some of them are also used for the beam energy feedback loops. The current DAQ system consists of the digital oscilloscopes and the VME computers. They are connected with the GPIB, and a signal from each electrode is analyzed with a predetermined response function once per second by a VME computer that is connected to the upper-layer control servers via Ethernet. The KEKB injector linac is planned to be upgraded to perform the simultaneous injection for 4-rings. In this operation mode, a fast DAQ system is strongly required. In the current system, maximum DAQ rate is strictly limited by the oscilloscope performance, and it should be improved for the 50-Hz measurement. For these reasons, we made the decision to replace the current DAQ system with the fast digital oscilloscope. In this paper, we will present the system description of the new DAQ system, and the detailed result of the performance test will be presented. | ||
| WPPB38 | Update on the CERN Computing and Network Infrastructure for Controls (CNIC) | 472 |
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| Over the last few years modern accelerator and experiment control systems have increasingly been based on commercial-off-the-shelf products (VME crates, PLCs, SCADA, etc.), on Windows or Linux PCs, and on communication infrastructures using Ethernet and TCP/IP. Despite the benefits coming with this (r)evolution, new vulnerabilities are inherited too: Worms and viruses spread within seconds via the Ethernet cable, and attackers are becoming interested in control systems. Unfortunately, control PCs cannot be patched as fast as office PCs. Even worse, vulnerability scans at CERN using standard IT tools have shown that commercial automation systems lack fundamental security precautions: Some systems crashed during the scan, others could easily be stopped or their process data be altered. During the two years following the presentation of the CNIC Security Policy at ICALEPCS2005, a “Defense-in-Depth” approach has been applied to protect CERN's control systems. This presentation will give a review of its thorough implementation and its deployment. Particularly, measures to secure the controls network and tools for user-driven management of Windows and Linux control PCs will be discussed. | ||
| WPPB39 | 130-MHz, 16-Bit Four-Channel Digitizer | 475 |
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| The PAD (Phase and Amplitude Detector) was designed to digitize high-speed analog input data with large dynamic range. Because of its high speed and high resolution processing capability, it has been useful to applications beyond measuring phase and amplitude of RF signals and klystron beam voltages. These applications include beam-position monitors, bunch-length monitors, and beam-charge monitors. The digitizer used is the Linear Technologies LTC2208. It was the first 16-bit digitizer chip on the market capable of running at 119MHz; it is specified to run up to 130MHz. For each channel, the 16-bit digitized signal from the LTC2208 is clocked into a 64k sample FIFO. Commercial FIFOs are available that store up to 256k samples in the same package. The data are then read from the FIFO into the Arcturus Coldfire uCDIMM. A CPLD is used to handle triggering, resetting the FIFO, interfacing the Coldfire processor to the 4 FIFOs, and interrupting the Coldfire processor. The processor runs RTEMS version 4.7 and EPICS 3.14.8.2. There is an optional add-on available that attaches to the QSPI port on the PAD for reading 8 slow, 24-bit analog signals. | ||
| WPPB40 | LCLS Beam-Position Monitor Data Acquisition System | 478 |
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| In order to determine the transversal LCLS beam position from the signals induced by the beam in four stripline pickup electrodes, the BPM electronics have to process four concurrent short RF bursts with a dynamic range > 60dB. An analog front end conditions the signals for subsequent acquisition with a waveform digitizer and also provides a calibration tone that can be injected into the system in order to compensate for gain variations and drift. Timing of the calibration pulser and switches, as well as control of various programmable attenuators, is provided by an FPGA. Because no COTS waveform digitizer with the desired performance (>14bit, ≥119MSPS) was available, the PAD digitizer (see separate contribution WPPB39) was selected. It turned out that the combination of a waveform digitizer with a low-end embedded CPU running a real-time OS (RTEMS) and control system (EPICS) is extremely flexible and could very easily be customized for our application. However, in order to meet the BPM real-time needs (readings in < 1ms), a second Ethernet interface was added to the PAD so that waveforms can be shipped, circumventing the ordinary TCP/IP stack on a dedicated link. |