Paper | Title | Other Keywords | Page |
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WEPD12 | A Large Channel Count Multi Client Data Acquisition System for Superconducting Magnet System of SST-1 | controls, plasma, monitoring, status | 26 |
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The magnet system of the steady-state superconducting tokamak-1 at the Institute for Plasma Research, Gandhinagar, India, consists of sixteen Toroidal field and nine poloidal field Superconducting coils together with a pair of resistive PF coils, an air core ohmic transformer and a pair of vertical field coils. These coils are instrumented with various cryogenic grade sensors and voltage taps to monitor it's operating status and health during different operational scenarios. A VME based data acquisition system with remote system architecture is implemented for data acquisition and control of the complete magnet operation. Client-Server based architecture is implemented with remote hardware configuration and continuous online/ offline monitoring. A JAVA based platform independent client application is developed for data analysis and data plotting. The server has multiple data pipeline architecture to send data to storage database, online plotting application, Numerical display screen, and run time calculation. This paper describes software architecture, design and implementation of the data acquisition system. | |||
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Poster WEPD12 [1.959 MB] | ||
THIB04 | Control System Interoperability, an Extreme Case: Merging DOOCS and TINE | controls, EPICS, status, electron | 115 |
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In controlling large facilities one is rarely able to manage all controllable elements via a common control system framework. When the standard framework must deal with numerous 'foreign' elements it is often worthwhile to adopt a new framework, rather than 'disguising' such components with a wrapper. The DOOCS[1] and TINE[2] control system frameworks fall into this scenario. Both systems have a device server oriented view, which made early mapping attempts (~2001) immediately successful. Transparent communication, however, is but a small (albeit important) part of the control system merger currently taking place. Both systems have well-established central services (e.g. archiving and alarms), and possess a general 'culture' which might dictate to a large extent how something is actually 'done'. The long term goal of the DOOCS/TINE merger is to be able to make use of any tool, from either the DOOCS or TINE toolbox, on any control system element. We report here on our progress to date, concentrating on the REGAE accelerator, and plans for the XFEL accelerator (to begin commissioning in 2015).
[1] http://doocs.desy.de [2] http://tine.desy.de |
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Slides THIB04 [3.167 MB] | ||
THPD22 | Controls for a 10 Petawatt Class Laser Facility | controls, laser, status, monitoring | 190 |
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Funding: Science & Technology Facilities Council, UK Computerised controls are vital to the operability and flexibility of large-scale physics facilities (such as accelerators, synchrotrons and high-power lasers) in providing fundamental services, for example, automatic configuring of specialist hardware, motion control, firing of shot sequences, enabling precision trigger distribution, vacuum monitoring and control, data acquisition and analysis. The proposed 10PW Laser facility, in line with other major physics facilities around the world, will require a complex computer control system. This is expected to be modeled on the existing Vulcan Laser[1] control system and consist of a dozen or so Windows based PCs each of which will be running a separate and dedicated application to control a particular area or function of the facility. This paper will present an overview of the existing Vulcan laser and provide a status report on the development towards the 10PW which will require the control system to be designed to allow autonomous operation of the 10PW facility as well as to be fully integrated with the existing Vulcan laser controls for combined and synchronized 10PW plus 1PW operations. [1] www.clf.stfc.ac.uk/Facilities/Vulcan/12248.aspx |
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Poster THPD22 [1.219 MB] | ||
THPD33 | Qt Based Control System Software for Low Energy Accelerator Facility | controls, ion, ion-source, GUI | 206 |
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Qt based control system software for low energy accelerating facility is operational in Trombay, BARC. LEAF is 50 keV negative ion electrostatic accelerator based on SNICS ion source. Control system uses Nokia Trolltech's QT 4.x API for control system software. Ni 6008 USB based multifunction cards has been used for control and read back field equipments such as power supplies, pumps, valves etc. Control system architecture is designed to be client server. Qt is chosen for its excellent GUI capability and platform independent nature. Control system follows client server architecture. This paper will describe the control system. | |||
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Poster THPD33 [2.966 MB] | ||
FRCA02 | Status Report, Future Plans and Maintenance Issues of VME Based Cryogenic Control System at IUAC | controls, cryogenics, linac, GUI | 245 |
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The Cryogenic Data Acquisition and Control system (CRYO-DACS) at IUAC was commissioned successfully in the year 2002 and has been continuously in operation since then with uptime better than 95%. The aim of CRYO-DACS is to control and acquire many analog and digital cryogenic parameters of super conducting LINAC and related equipments like beam-line cryostats, helium compressors, cryogenic distribution etc. The complete system is implemented using two VME crates, housing I/O modules, placed far apart and interconnected using Ethernet. The software implementation and maintenance have also been trouble-free which used IOWORKS as the development tool for embedded CPUs running VxWORKS. The OPC Client was developed using VB6 & MSACCESS RDBMS for data logging, viewing and trending under Windows 2000 stable server. In summary, this paper will elaborate the implementation, use and related failures faced for last 10 years and the subsequent corrective actions taken to keep the system running for such a long time round the clock along with some future plans. | |||
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Slides FRCA02 [4.305 MB] | ||
FRCC03 | Development and Performance Analysis of EPICS Channel Access Server on FPGA based Soft-core Processor | EPICS, controls, lattice | 274 |
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A soft core processor is a flexible hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an FPGA as opposed to a hard core processor which is fixed in silicon. Combined with an on-board ethernet port, the technology incorporates integrating the IOC and digital control hardware within a single FPGA thus reducing the overall hardware complexities of field devices. In this paper, the technical details of porting EPICS Channel Access Server on MicroBlaze soft-core processor are explained. The EPICS performance on the Microblaze processor is analyzed. For this, the CPU load and server processing time for different numbers of Process Variables (PVs) have been studied for this platform. On the basis of the analysis, critical parameters of EPICS on this embedded platform have been derived and a few modifications in the channel access protocol are proposed for MicroBlaze soft-core processor. | |||
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Slides FRCC03 [2.238 MB] | ||
FRCC04 | Digital Pulse Processing Techniques for High Resolution Amplitude Measurement of Radiation Detector | radiation, shielding | 279 |
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The digital pulse processing techniques for high resolution amplitude measurement of radiation detector pulse is an effective replacement of expensive and bulky analog processing as the digital domain offers higher channel density and at the same time it is cheaper. We have demonstrated a prototype digital setup with high-speed sampling ADC with sampling frequency of 80-125 MHz followed by series of IIR filters for pulse shaping in a trigger-less acquisition mode. The IIR filters, peak detection algorithm and the data write-out logic was written on VHDL and implemented on FPGA. We used CAMAC as the read out platform. In conjunction with the full hardware implementation we also used a mixed-platform with VME digitizer card with raw-sample read out using C code. The rationale behind this mixed platform is to test out various filter algorithms quickly on C and also to benchmark the performance of the chip level ADCs against the standard commercial digitizer in terms of noise or resolution. The paper describes implementation of both the methods with performance obtained in both the methods. | |||
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Slides FRCC04 [1.248 MB] | ||