PCaPAC2012 - List of Keywords (shielding)

Paper	Title	Other Keywords	Page
FRCC04	Digital Pulse Processing Techniques for High Resolution Amplitude Measurement of Radiation Detector	radiation, target	279
	P. Singhai, P. Dhara, A. Roy VECC, Kolkata, India S. Chatterjee HITK, Kolkata, India
	The digital pulse processing techniques for high resolution amplitude measurement of radiation detector pulse is an effective replacement of expensive and bulky analog processing as the digital domain offers higher channel density and at the same time it is cheaper. We have demonstrated a prototype digital setup with high-speed sampling ADC with sampling frequency of 80-125 MHz followed by series of IIR filters for pulse shaping in a trigger-less acquisition mode. The IIR filters, peak detection algorithm and the data write-out logic was written on VHDL and implemented on FPGA. We used CAMAC as the read out platform. In conjunction with the full hardware implementation we also used a mixed-platform with VME digitizer card with raw-sample read out using C code. The rationale behind this mixed platform is to test out various filter algorithms quickly on C and also to benchmark the performance of the chip level ADCs against the standard commercial digitizer in terms of noise or resolution. The paper describes implementation of both the methods with performance obtained in both the methods.
	Slides FRCC04 [1.248 MB]

Paper

Title

Other Keywords

Page

FRCC04

Digital Pulse Processing Techniques for High Resolution Amplitude Measurement of Radiation Detector

radiation, target

279

P. Singhai, P. Dhara, A. Roy
VECC, Kolkata, India
S. Chatterjee
HITK, Kolkata, India

The digital pulse processing techniques for high resolution amplitude measurement of radiation detector pulse is an effective replacement of expensive and bulky analog processing as the digital domain offers higher channel density and at the same time it is cheaper. We have demonstrated a prototype digital setup with high-speed sampling ADC with sampling frequency of 80-125 MHz followed by series of IIR filters for pulse shaping in a trigger-less acquisition mode. The IIR filters, peak detection algorithm and the data write-out logic was written on VHDL and implemented on FPGA. We used CAMAC as the read out platform. In conjunction with the full hardware implementation we also used a mixed-platform with VME digitizer card with raw-sample read out using C code. The rationale behind this mixed platform is to test out various filter algorithms quickly on C and also to benchmark the performance of the chip level ADCs against the standard commercial digitizer in terms of noise or resolution. The paper describes implementation of both the methods with performance obtained in both the methods.

Slides FRCC04 [1.248 MB]