ICALEPCS2021 - List of Authors (Adrianek, K.)

Paper	Title	Page
THBR02	White Rabbit and MTCA.4 Use in the LLRF Upgrade for CERN’s SPS	847
	T. Włostowski, K. Adrianek, M. Arruat, P. Baudrenghien, A.C. Butterworth, G. Daniluk, J. Egli, J.R. Gill, T. Gingold, J.D. González Cobas, G. Hagmann, P. Kuzmanović, D. Lampridis, M.M. Lipiński, S. Novel González, J.P. Palluel, M. Rizzi, A. Spierer, M. Sumiński, A. Wujek CERN, Geneva, Switzerland
	The Super Proton Synchrotron (SPS) Low-level RF (LLRF) system at CERN was completely revamped in 2020. In the old system, the digital signal processing was clocked by a submultiple of the RF. The new system uses a fixed-frequency clock derived from White Rabbit (WR). This triggered the development of an eRTM module for generating very precise clock signals to be fed to the optional RF backplane in MTCA.4 crates. The eRTM14/15 sandwich of modules implements a WR node delivering clock signals with a jitter below 100 fs. WR-clocked RF synthesis inside the FPGA makes it simple to reproduce the RF elsewhere by broadcasting the frequency-tuning words over the WR network itself. These words are received by the WR2RF-VME module and used to produce beam-synchronous signals such as the bunch clock and the revolution tick. This paper explains the general architecture of this new LLRF system, highlighting the role of WR-based synchronization. It then goes on to describe the hardware and gateware designs for both modules, along with their supporting software. A recount of our experience with the deployment of the MTCA.4 platform is also provided.
	Slides THBR02 [0.981 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THBR02
About •	Received ※ 12 October 2021 Revised ※ 24 October 2021 Accepted ※ 03 January 2022 Issue date ※ 28 February 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPV033	Reusable Real-Time Software Components for the SPS Low Level RF Control System	939
	M. Sumiński, K. Adrianek, B. Bielawski, A.C. Butterworth, J. Egli, G. Hagmann, P. Kuzmanović, S. Novel González, A. Rey, A. Spierer CERN, Geneva, Switzerland
	In 2021 the Super Proton Synchrotron has been recommissioned after a complete renovation of its low level RF system (LLRF). The new system has largely moved to digital signal processing implemented as a set of functional blocks (IP cores) in Field Programmable Gate Arrays (FPGAs) with associated software to control them. Some of these IP cores provide generic functionalities such as timing, function generation, data resampling and signal acquisition, and are reused in several components, with a potential application in other accelerators. To take full advantage of the modular approach, IP core flexibility must be complemented by the software stack. In this paper we present steps we have taken to reach this goal from the software point of view, and describe the custom tools and procedures used to implement the various software layers.
	Poster THPV033 [1.234 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THPV033
About •	Received ※ 09 October 2021 Accepted ※ 25 February 2022 Issue date ※ 28 February 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

White Rabbit and MTCA.4 Use in the LLRF Upgrade for CERN’s SPS

847

T. Włostowski, K. Adrianek, M. Arruat, P. Baudrenghien, A.C. Butterworth, G. Daniluk, J. Egli, J.R. Gill, T. Gingold, J.D. González Cobas, G. Hagmann, P. Kuzmanović, D. Lampridis, M.M. Lipiński, S. Novel González, J.P. Palluel, M. Rizzi, A. Spierer, M. Sumiński, A. Wujek
CERN, Geneva, Switzerland

The Super Proton Synchrotron (SPS) Low-level RF (LLRF) system at CERN was completely revamped in 2020. In the old system, the digital signal processing was clocked by a submultiple of the RF. The new system uses a fixed-frequency clock derived from White Rabbit (WR). This triggered the development of an eRTM module for generating very precise clock signals to be fed to the optional RF backplane in MTCA.4 crates. The eRTM14/15 sandwich of modules implements a WR node delivering clock signals with a jitter below 100 fs. WR-clocked RF synthesis inside the FPGA makes it simple to reproduce the RF elsewhere by broadcasting the frequency-tuning words over the WR network itself. These words are received by the WR2RF-VME module and used to produce beam-synchronous signals such as the bunch clock and the revolution tick. This paper explains the general architecture of this new LLRF system, highlighting the role of WR-based synchronization. It then goes on to describe the hardware and gateware designs for both modules, along with their supporting software. A recount of our experience with the deployment of the MTCA.4 platform is also provided.

Slides THBR02 [0.981 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THBR02

About •

Received ※ 12 October 2021 Revised ※ 24 October 2021 Accepted ※ 03 January 2022 Issue date ※ 28 February 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPV033

Reusable Real-Time Software Components for the SPS Low Level RF Control System

939

M. Sumiński, K. Adrianek, B. Bielawski, A.C. Butterworth, J. Egli, G. Hagmann, P. Kuzmanović, S. Novel González, A. Rey, A. Spierer
CERN, Geneva, Switzerland

In 2021 the Super Proton Synchrotron has been recommissioned after a complete renovation of its low level RF system (LLRF). The new system has largely moved to digital signal processing implemented as a set of functional blocks (IP cores) in Field Programmable Gate Arrays (FPGAs) with associated software to control them. Some of these IP cores provide generic functionalities such as timing, function generation, data resampling and signal acquisition, and are reused in several components, with a potential application in other accelerators. To take full advantage of the modular approach, IP core flexibility must be complemented by the software stack. In this paper we present steps we have taken to reach this goal from the software point of view, and describe the custom tools and procedures used to implement the various software layers.

Poster THPV033 [1.234 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THPV033

About •

Received ※ 09 October 2021 Accepted ※ 25 February 2022 Issue date ※ 28 February 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)