JACoW is a publisher in Geneva, Switzerland that publishes the proceedings of accelerator conferences held around the world by an international collaboration of editors.
@inproceedings{suminski:icalepcs2021-thpv033,
author = {M. Sumiński and K. Adrianek and B. Bielawski and A.C. Butterworth and J. Egli and G. Hagmann and P. Kuzmanović and S. Novel González and A. Rey and A. Spierer},
% author = {M. Sumiński and K. Adrianek and B. Bielawski and A.C. Butterworth and J. Egli and G. Hagmann and others},
% author = {M. Sumiński and others},
title = {{Reusable Real-Time Software Components for the SPS Low Level RF Control System}},
booktitle = {Proc. ICALEPCS'21},
pages = {939--941},
eid = {THPV033},
language = {english},
keywords = {hardware, software, controls, interface, Linux},
venue = {Shanghai, China},
series = {International Conference on Accelerator and Large Experimental Physics Control Systems},
number = {18},
publisher = {JACoW Publishing, Geneva, Switzerland},
month = {03},
year = {2022},
issn = {2226-0358},
isbn = {978-3-95450-221-9},
doi = {10.18429/JACoW-ICALEPCS2021-THPV033},
url = {https://jacow.org/icalepcs2021/papers/thpv033.pdf},
abstract = {{In 2021 the Super Proton Synchrotron has been recommissioned after a complete renovation of its low level RF system (LLRF). The new system has largely moved to digital signal processing implemented as a set of functional blocks (IP cores) in Field Programmable Gate Arrays (FPGAs) with associated software to control them. Some of these IP cores provide generic functionalities such as timing, function generation, data resampling and signal acquisition, and are reused in several components, with a potential application in other accelerators. To take full advantage of the modular approach, IP core flexibility must be complemented by the software stack. In this paper we present steps we have taken to reach this goal from the software point of view, and describe the custom tools and procedures used to implement the various software layers.}},
}