Paper |
Title |
Page |
WEODN1 |
Overview of System Specifications for Bunch by Bunch Feedback Systems |
1475 |
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- D. Teytelman
Dimtel, San Jose, USA
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Bunch-by-bunch feedback control of coupled-bunch instabilities has become a ubiquitous feature of storage rings, light sources and colliders. Specifying the requirements for these systems demands knowledge of the instability sources and the accelerator operating parameter space. System requirements include the necessary loop gain and bandwidth, kick voltage, and the overall noise floor. Based on these specifications one can select the system BPMs, processing algorithms, power amplifiers and kickers and make tradeoffs of system cost against necessary performance. Through the use of analytical and experimental techniques this talk will illustrate practical and intelligent choices in this specification process. The approach involves experimental characterization of the accelerator at low or moderate beam currents. Measurements are used to calibrate a parameterized analytical beam dynamics model which can be then extrapolated to nominal beam currents with confidence. The speaker will present example results from several recent installations, highlighting the measurements, the model predictions, and the achieved system performance.
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Slides WEODN1 [1.755 MB]
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WEODN2 |
KEK ATF Beam Instrumentation Program |
1480 |
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- N. Terunuma
KEK, Ibaraki, Japan
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The Accelerator Test Facility (ATF) in KEK is a research center for studies on issues concerning the injector, damping ring, and beam delivery system for the ILC. It comprises a multibunch-capable RF gun, a 1.3 GeV electron linac, a damping ring, and a test beam line for ILC final focus system (ATF2). Goals of ATF/ATF2 are the achievement of 2 pm vertical emittance, demonstration of a ILC like multi-bunch extraction, achievement of the 37 nm vertical beam size, and stabilization of such beam in a few nano meter level. These targets are supported by R&Ds, such as upgrade of DR BPMs, fast kicker, cavity BPMs, laser-wire, intra-train feedback system (FONT) and a Laser-fringe beam size monitor. To continue providing vital opportunities for accelerator development with the world community, the international collaboration was established.
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Slides WEODN2 [7.631 MB]
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WEODN3 |
Performance Optimization for the LNLS Fast Orbit Feedback System |
1485 |
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- D.O. Tavares, S.R. Marques
LNLS, Campinas, Brazil
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The Brazilian Synchrotron Light Laboratory (LNLS) has recently commissioned a Fast Orbit Feedback System for its 1.37 GeV third-generation UVX Storage Ring. This paper presents the optimization work which was carried out using the new hardware capabilities. Well known strategies such as singular values conditioning for correction matrix, dynamic control by means of PID or IMC controllers and EVC (Eigenvector constrained) method for minimizing position error in source points were explored. The problem of actuator limitations (saturation and slew rate) was also investigated, providing a new front line for improving orbit stability through feedback.
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Slides WEODN3 [1.114 MB]
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WEODN4 |
NSLS-II Fast Orbit Feedback with Individual Eigenmode Compensation |
1488 |
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- Y. Tian, L.-H. Yu
BNL, Upton, Long Island, New York, USA
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This paper presents the NSLS-II fast orbit feedback system with individual eigenmode compensation. The fast orbit feedback system is a typical multiple-input and multiple-output (MIMO) system. Traditional singular value decomposition (SVD) based fast orbit feedback systems treat each eigenmode the same and the same compensation algorithm is applied to all the eigenmodes. In reality, a MIMO system will have different frequency responses for different eigenmodes and thus it is desirable to design different compensation for each eigenmode. The difficulty with this approach comes from the large amount of computation that needs to be done within the time budget of the orbit feedback system. We designed and implemented the NSLS-II fast orbit feedback (FOFB) system with individual eigenmode compensation by taking advantage of the parallel computation capability of field programmable gate array (FPGA) chips.
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Slides WEODN4 [1.064 MB]
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