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Paper Title Other Keywords Page
TU201 Linac R&D for the ILC Technical Design Report linac, cryomodule, collider, cavity 359
  • M.C. Ross
    Fermilab, Batavia

The International Linear Collider (ILC) Technical Design Report (TDR) is scheduled for publication in 2012. The TDR will include an updated ILC baseline technical design description, results from critical R&D programs in support of key parameter choices, and one or more models for a Project Implementation Plan with an associated value estimate. The focus of linac R&D is to:

  1. achieve the specified superconducting rf cavity accelerating gradient of 35 MV/m with a corresponding production yield,
  2. design and test cryomodule assemblies that include "plug-compatible" sub-components with specified interfaces, and
  3. demonstrate system performance with nominal ILC high intensity beams.
In keeping with the international nature of the project, R&D is underway at ILC partner institutions with results and infrastructure that are shared throughout the project effort. This paper describes the technical challenges to be addressed and summarizes ongoing activities and plans.


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TUP021 Digitally Controlled High Availability Power Supply power-supply, controls, collider, diagnostics 437
  • D.J. MacNair
    SLAC, Menlo Park, California

Funding: US DOE
This paper reports the design and test results on novel topology, high-efficiency, and low operating temperature, 1,320-watt power modules for high availability power supplies. The modules permit parallel operation for N+1 redundancy with hot swap capability. An embedded DSP provides intelligent start-up and shutdown, output regulation, general control and fault detection. PWM modules in the DSP drive the FET switches at 20 to 100 kHz. The DSP also ensures current sharing between modules, synchronized switching, and soft start up for hot swapping. The module voltage and current have dedicated ADCs (>200 kS/sec) to provide pulse-by-pulse output control. A Dual CAN bus interface provides for low cost redundant control paths. Over-rated module components provide high reliability and high efficiency at full load. Low on-resistance FETs replace conventional diodes in the buck regulator. Saturable inductors limit the FET reverse diode current during switching. The modules operate in a two-quadrant mode, allowing bipolar output from complimentary module groups. Controllable, low resistance FETs at the input and output provide fault isolation and allow module hot swapping.

TUP058 A Kicker Driver Exploiting Drift Step Recovery Diodes for the International Linear Collider kicker, damping, high-voltage, instrumentation 536
  • F.O. Arntz, M.P.J. Gaudreau, A. Kardo-Sysoev, M.K. Kempkes, A. Krasnykh
    Diversified Technologies, Inc., Bedford, Massachusetts

Funding: U.S. Department of Energy SBIR Program
Diversified Technologies, Inc. (DTI) is developing a driver for a kicker strip-line deflector which inserts and extracts charge bunches to and from the electron and positron damping rings of the International Linear Collider. The kicker driver must drive a 50 Ω terminated TEM deflector blade at 10 kV with 2 ns flat-topped pulses, which according to the ILC pulsing protocol, bursts pulses at a 3 MHz rate within one-millisecond bursts occurring at a 5 Hz rate. The driver must also effectively absorb high-order mode signals emerging from the deflector. In this paper, DTI will describe current progress utilizing a combination of high voltage DSRDs (Drift Step Recovery Diodes) and high voltage MOSFETs. The MOSFET array switch, without the DSRDs, is itself suitable for many accelerator systems with 10 - 100 ns kicker requirements. DTI has designed and demonstrated the key elements of a solid state kicker driver which both meets the ILC requirements, is suitable for a wide range of kicker driver applications. Full scale development and test are exptected to occur in Phase II of this DOE SBIR effort, with a full scale demonstration scheduled in 2009.

THP053 The Status of Nextef; The X-band Test Facility in KEK klystron, collider, controls, status 906
  • S. Matsumoto, M. Akemoto, S. Fukuda, T. Higo, N. Kudoh, H. Matsushita, H. Nakajima, T. Shidara, K. Yokoyama, M. Yoshida
    KEK, Ibaraki

Nextef is a new X-band (11.4GHz) test facility in KEK. All of the key devices of this facility are from our old X-band Test Facility(XTF). By combining the power from two klystrons, 100 MW maximum X-band rf power is produced and 75MW is available in the bunker where the high power test of the high gradient accelerator structures will be done. The commissioning of the facility for the structure testing has almost done. The status of the facilityis is reported.

THP106 High Speed Data Acquisition System Using FPGA for LLRF Measurement and Control controls, LLRF, low-level-rf, superconducting-cavity 1042
  • H. Katagiri, S. Fukuda, T. Matsumoto, S. Michizono, T. Miura, Y. Yano, M. Yoshida
    KEK, Ibaraki

Recently, FPGA technology is widely used for the accelerator control owing to its fast digital processing. We have been developing several applications for LLRF control and measurement using commercial and custom-made FPGA board. XtremeDSP(the commercial FPGA board equipped two ADCs and two DACs) is mainly used for the performance evaluation of STF(Superconducting RF Test Facility) LLRF. Installing the custom-made FPGA board equipped with ten ADCs and two DACs is considering for up-grade of the rf driver and rf monitoring system in the injector linac. Development of the high-speed data acquisition system that combines commercial FPGA board ML555 and FastADC(ADS5474 14bit, 400MS/s) is carried out. Result of those data acquisition systems will be summarized.