ICALEPCS2017 - List of Authors (Czuba, K.)

Paper	Title	Page
TUPHA178	Abstracted Hardware and Middleware Access in Control Applications	840
	M. Killenberg, M. Heuer, M. Hierholzer, T. Kozak, L.P. Petrosyan, Ch. Schmidt, N. Shehzad, G. Varghese, M. Viti DESY, Hamburg, Germany K. Czuba, A. Dworzanski Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland C.P. Iatrou, J. Rahm TU Dresden, Dresden, Germany M. Kuntzsch, R. Steinbrück HZDR, Dresden, Germany S. Marsching Aquenos GmbH, Baden-Baden, Germany A. Piotrowski FastLogic Sp. z o.o., Łódź, Poland P. Prędki Rapid Development, Łódź, Poland
	Hardware access often brings implementation details into a control application, which are subsequently published to the control system. Experience at DESY has shown that it is beneficial for the software quality to use a high level of abstraction from the beginning of a project. Some hardware registers for instance can immediately be treated as process variables if an appropriate library is taking care of most of the error handling. Other parts of the hardware need an additional layer to match the abstraction level of the application. Like this development cycles can be shortened and the code is easier to read and maintain because the logic focuses on what is done, not how it is done. We present the abstraction concept we are using, which is not only unifying the access to hardware but also how process variables are published via the control system middleware.
	Poster TUPHA178 [0.875 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA178
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THPHA081	LO Board for 704.42 MHz Cavity Simulator for ESS	1573
	I. Rutkowski, K. Czuba, M.G. Grzegrzolka Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
	Funding: Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2016/03 This paper describes the requirements, architecture, and measurements results of the local oscillator (LO) board prototype. The design will provide low phase noise clock and heterodyne signals for the 704.42 MHz Cavity Simulator for the European Spallation Source. A field detection has critical influence on the simulation's performance and its quality depends on the quality of the two aforementioned signals. The clock frequency is a subharmonic of the reference frequency and choice of the frequency divider generating the clock signals is discussed. The performance of selected dividers was compared. The LO frequency must be synthesized and frequency synthesis schemes are investigated. Critical components used in the direct analog scheme are identified and their selection criteria were given.
	Poster THPHA081 [1.406 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA081
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THPHA090	Channel Selection Switch for the Redundant 1.3 GHz Master Oscillator of the European XFEL	1590
	B. Gąsowski, K. Czuba, L.Z. Zembala Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland H. Schlarb DESY, Hamburg, Germany
	Funding: Research supported by Polish Ministry of Science and Higher Education, founds for international co-financed projects for years 2016 and 2017. The phase reference signal reliability is of utmost importance for continuous operation of the European XFEL machine. Since even very short interruption or glitch in the reference signal might break the precise synchronisation between subsystems, it is desirable to minimize probability of such events. While master oscillators often have a hot-spare to speed-up recovery after a failure, whether switched manually or electronically, it does not save from time-consuming resynchronisation. Our experience from testing and commissioning E-XFEL 1.3 GHz Master Oscillator (MO) shows that a struggle to achieve demanding phase-noise requirements might negatively impact reliability of the system. In this paper we present an approach which allows for quick switching between independent reference generation channels while maintaining continuity of the output signal. This is a first step towards autonomous redundancy solution for the E-XFEL MO which will maintain continuous reference signal even in case of a failure of one of the generation channels.
	Poster THPHA090 [1.155 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA090
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THPHA092	Optimisation of a Low-Noise 1.3 GHz PLL Frequency Synthesizer for the European XFEL	1595
	S. Hanasz, K. Czuba, B. Gąsowski, L.Z. Zembala Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland H. Schlarb DESY, Hamburg, Germany
	Funding: Research supported by Polish Ministry of Science and Higher Education, founds for international co-financed projects for year 2017. The Master Oscillator system of the European XFEL was built using frequency synthesis techniques that were found to have the best phase noise performance. This includes low noise frequency multipliers and nonÂmultiplying phase lock loops, incorporated in the system to shape its output phase noise spectrum. Jitter of the output signal strongly depends on phase noise transmittance of the PLL and suboptimal design can worsen it by orders of magnitude. Taking into consideration that the PLL open loop transmittance usually can be shaped in multiple ways, and that the accurate phase noise measurements can easily take more than 30 minutes, designing an automated tool becomes a necessity. For this purpose an approach to the tuning system construction was chosen in order to make the phase noise optimisation process simpler. This paper describes the optimisation of PLL synthesizer phase noise, done to improve the performance of the European XFEL MO. We present the phase noise optimisation process and achieved results.
	Poster THPHA092 [1.393 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA092
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THPHA123	Concept of Cavity Simulator for European Spallation Source	1666
	M.G. Grzegrzolka, K. Czuba, I. Rutkowski Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
	At the European Spallation Source it is foreseen to use around 120 superconducting cavities operating at 704.42 MHz. Each cavity will require an individual LLRF control system, that needs to be tested before the installation inside the accelerator. Testing of all systems using the real superconducting cavities would be very expensive and in case of a failure can lead to serious damages. To lower the testing cost and avoid potential risks it is planned to design and build a device that simulates the behavior of a superconducting cavity. The cavity simulator will utilize fast data converters equipped with an RF front-end and a digital signal processing unit based on a high performance FPGA. In this paper conceptual design of hardware and firmware will be presented.
	Poster THPHA123 [1.500 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA123
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Abstracted Hardware and Middleware Access in Control Applications

840

M. Killenberg, M. Heuer, M. Hierholzer, T. Kozak, L.P. Petrosyan, Ch. Schmidt, N. Shehzad, G. Varghese, M. Viti
DESY, Hamburg, Germany
K. Czuba, A. Dworzanski
Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
C.P. Iatrou, J. Rahm
TU Dresden, Dresden, Germany
M. Kuntzsch, R. Steinbrück
HZDR, Dresden, Germany
S. Marsching
Aquenos GmbH, Baden-Baden, Germany
A. Piotrowski
FastLogic Sp. z o.o., Łódź, Poland
P. Prędki
Rapid Development, Łódź, Poland

Hardware access often brings implementation details into a control application, which are subsequently published to the control system. Experience at DESY has shown that it is beneficial for the software quality to use a high level of abstraction from the beginning of a project. Some hardware registers for instance can immediately be treated as process variables if an appropriate library is taking care of most of the error handling. Other parts of the hardware need an additional layer to match the abstraction level of the application. Like this development cycles can be shortened and the code is easier to read and maintain because the logic focuses on what is done, not how it is done. We present the abstraction concept we are using, which is not only unifying the access to hardware but also how process variables are published via the control system middleware.

Poster TUPHA178 [0.875 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA178

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA081

LO Board for 704.42 MHz Cavity Simulator for ESS

1573

I. Rutkowski, K. Czuba, M.G. Grzegrzolka
Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland

Funding: Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2016/03
This paper describes the requirements, architecture, and measurements results of the local oscillator (LO) board prototype. The design will provide low phase noise clock and heterodyne signals for the 704.42 MHz Cavity Simulator for the European Spallation Source. A field detection has critical influence on the simulation's performance and its quality depends on the quality of the two aforementioned signals. The clock frequency is a subharmonic of the reference frequency and choice of the frequency divider generating the clock signals is discussed. The performance of selected dividers was compared. The LO frequency must be synthesized and frequency synthesis schemes are investigated. Critical components used in the direct analog scheme are identified and their selection criteria were given.

Poster THPHA081 [1.406 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA081

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA090

Channel Selection Switch for the Redundant 1.3 GHz Master Oscillator of the European XFEL

1590

B. Gąsowski, K. Czuba, L.Z. Zembala
Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
H. Schlarb
DESY, Hamburg, Germany

Funding: Research supported by Polish Ministry of Science and Higher Education, founds for international co-financed projects for years 2016 and 2017.
The phase reference signal reliability is of utmost importance for continuous operation of the European XFEL machine. Since even very short interruption or glitch in the reference signal might break the precise synchronisation between subsystems, it is desirable to minimize probability of such events. While master oscillators often have a hot-spare to speed-up recovery after a failure, whether switched manually or electronically, it does not save from time-consuming resynchronisation. Our experience from testing and commissioning E-XFEL 1.3 GHz Master Oscillator (MO) shows that a struggle to achieve demanding phase-noise requirements might negatively impact reliability of the system. In this paper we present an approach which allows for quick switching between independent reference generation channels while maintaining continuity of the output signal. This is a first step towards autonomous redundancy solution for the E-XFEL MO which will maintain continuous reference signal even in case of a failure of one of the generation channels.

Poster THPHA090 [1.155 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA090

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA092

Optimisation of a Low-Noise 1.3 GHz PLL Frequency Synthesizer for the European XFEL

1595

S. Hanasz, K. Czuba, B. Gąsowski, L.Z. Zembala
Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
H. Schlarb
DESY, Hamburg, Germany

Funding: Research supported by Polish Ministry of Science and Higher Education, founds for international co-financed projects for year 2017.
The Master Oscillator system of the European XFEL was built using frequency synthesis techniques that were found to have the best phase noise performance. This includes low noise frequency multipliers and nonÂmultiplying phase lock loops, incorporated in the system to shape its output phase noise spectrum. Jitter of the output signal strongly depends on phase noise transmittance of the PLL and suboptimal design can worsen it by orders of magnitude. Taking into consideration that the PLL open loop transmittance usually can be shaped in multiple ways, and that the accurate phase noise measurements can easily take more than 30 minutes, designing an automated tool becomes a necessity. For this purpose an approach to the tuning system construction was chosen in order to make the phase noise optimisation process simpler. This paper describes the optimisation of PLL synthesizer phase noise, done to improve the performance of the European XFEL MO. We present the phase noise optimisation process and achieved results.

Poster THPHA092 [1.393 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA092

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA123

Concept of Cavity Simulator for European Spallation Source

1666

M.G. Grzegrzolka, K. Czuba, I. Rutkowski
Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland

At the European Spallation Source it is foreseen to use around 120 superconducting cavities operating at 704.42 MHz. Each cavity will require an individual LLRF control system, that needs to be tested before the installation inside the accelerator. Testing of all systems using the real superconducting cavities would be very expensive and in case of a failure can lead to serious damages. To lower the testing cost and avoid potential risks it is planned to design and build a device that simulates the behavior of a superconducting cavity. The cavity simulator will utilize fast data converters equipped with an RF front-end and a digital signal processing unit based on a high performance FPGA. In this paper conceptual design of hardware and firmware will be presented.

Poster THPHA123 [1.500 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA123

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)