IPAC2017 - List of Keywords (interlocks)

Paper	Title	Other Keywords	Page
WEPVA110	Analysis and Operational Feedback on the New Design of the High Energy Beam Dump in the CERN SPS	vacuum, operation, simulation, shielding	3524
	P. Rios Rodriguez, J.A. Briz Monago, M. Calviani, K. Cornelis, S. De Man, R. Esposito, S.S. Gilardoni, B. Goddard, J.L. Grenard, D. Grenier, M. Grieco, J. Humbert, V. Kain, F.M. Leaux, C. Pasquino, A. Perillo-Marcone, J.R.F. Poujol, S. Sgobba, D. Steyart, F.M. Velotti, V. Vlachoudis CERN, Geneva, Switzerland
	CERN's Super Proton Synchrotron (SPS) high-energy internal dump (Target Internal Dump Vertical Graphite, known as TIDVG) is required to intercept beams from 10² to 450 GeV. The equipment installed in 2014 (TIDVG#3) featured an absorbing core composed of different materials surrounded by a water-cooled copper jacket, which hold the UHV of the machine. An inspection of a previous equipment (TIDVG#2) in 2013 revealed significant beam induced damage to the aluminium section of the dump, which required imposing operational limitations to minimise the risk of reproducing this phenomenon. Additionally, in 2016 a vacuum leak was detected in the dump assembly, which imposed further limitations, i.e. a reduction of the beam intensity that could be dumped per SPS supercycle. This paper presents a new design (TIDVG#4), which focuses on improving the operational robustness of the device. Moreover, thanks to the added instrumentation, a careful analysis of its performance (both experimentally and during operation) will be possible. These studies will help validating technical solutions for the design of the future SPS dump to be installed during CERN's Long Shutdown 2 in 2020 (TIDVG#5).
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2017-WEPVA110
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THPAB134	Latest Development of the ALBA DLLRF	cavity, LLRF, beam-loading, rf-amplifier	4034
	A. Salom, B. Bravo, M. Broseta, E. Morales, J.R. Ocampo, F. Pérez, P. Solans ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain
	The Digital LLRF of ALBA has been implemented using commercial cPCI boards with Virtex-4 FPGA, fast ADCs and fast DACs. The firmware of the FPGA is based on IQ demodulation technique and the main feed-back loops adjust the phase and amplitude of the cavity voltage and also the resonance frequency of the cavity. This paper summarizes the latest LLRF developments done to improve performance of the RF systems and beam stability, including feed-forward loops based on phase modulation to compensate disturbances due to RF trip, beam loading compensation and Power Unbalance Compensation Loop for RF amplifiers Combination.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2017-THPAB134
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THPAB135	Digital LLRF for MAX IV	cavity, LLRF, FPGA, vacuum	4037
	A. Salom, F. Pérez ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain Å. Andersson, R. Lindvall, L. Malmgren, A.M. Milan, A.M. Mitrovic MAX IV Laboratory, Lund University, Lund, Sweden
	The MAX IV facility consists of a 3 GeV Storage Ring(SR), a 1.5 GeV SR, and a linear accelerator (fed by two guns) that serves as a full-energy injector to the rings, but also as a driver for the Short Pulse Facility. The RF systems of the two SRs work at 100MHz. There are 6 normal conducting capacity loaded accelerating cavities and three Landau passive cavities in the 3GeV SR. In the 1.5GeV SR there are two accelerating cavities and two Landau cavities with the same characteristics. Each of these cavities is fed by a modular 60kW SSA. In the 3 GeV SR the power will be doubled by adding a second SSA when required. A digital Low Level RF system has been developed using commercial uTCA boards, with a Virtex-6 FPGA mother board (Perseus 601X) and two double stack FMC boards with fast ADCs and DACs. The large capabilities of state-of-the-art FPGAs allowed including the control of two normal conducing cavities and two landau cavities in one single LLRF system, reducing the development costs. Other utilities like the handling of fast interlocks and post-mortem analysis were also added to this system. This paper summarizes the main capabilities and performance of this DLLRF.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2017-THPAB135
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Paper

Title

Other Keywords

Page

WEPVA110

Analysis and Operational Feedback on the New Design of the High Energy Beam Dump in the CERN SPS

vacuum, operation, simulation, shielding

3524

P. Rios Rodriguez, J.A. Briz Monago, M. Calviani, K. Cornelis, S. De Man, R. Esposito, S.S. Gilardoni, B. Goddard, J.L. Grenard, D. Grenier, M. Grieco, J. Humbert, V. Kain, F.M. Leaux, C. Pasquino, A. Perillo-Marcone, J.R.F. Poujol, S. Sgobba, D. Steyart, F.M. Velotti, V. Vlachoudis
CERN, Geneva, Switzerland

CERN's Super Proton Synchrotron (SPS) high-energy internal dump (Target Internal Dump Vertical Graphite, known as TIDVG) is required to intercept beams from 10² to 450 GeV. The equipment installed in 2014 (TIDVG#3) featured an absorbing core composed of different materials surrounded by a water-cooled copper jacket, which hold the UHV of the machine. An inspection of a previous equipment (TIDVG#2) in 2013 revealed significant beam induced damage to the aluminium section of the dump, which required imposing operational limitations to minimise the risk of reproducing this phenomenon. Additionally, in 2016 a vacuum leak was detected in the dump assembly, which imposed further limitations, i.e. a reduction of the beam intensity that could be dumped per SPS supercycle. This paper presents a new design (TIDVG#4), which focuses on improving the operational robustness of the device. Moreover, thanks to the added instrumentation, a careful analysis of its performance (both experimentally and during operation) will be possible. These studies will help validating technical solutions for the design of the future SPS dump to be installed during CERN's Long Shutdown 2 in 2020 (TIDVG#5).

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2017-WEPVA110

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPAB134

Latest Development of the ALBA DLLRF

cavity, LLRF, beam-loading, rf-amplifier

4034

A. Salom, B. Bravo, M. Broseta, E. Morales, J.R. Ocampo, F. Pérez, P. Solans
ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain

The Digital LLRF of ALBA has been implemented using commercial cPCI boards with Virtex-4 FPGA, fast ADCs and fast DACs. The firmware of the FPGA is based on IQ demodulation technique and the main feed-back loops adjust the phase and amplitude of the cavity voltage and also the resonance frequency of the cavity. This paper summarizes the latest LLRF developments done to improve performance of the RF systems and beam stability, including feed-forward loops based on phase modulation to compensate disturbances due to RF trip, beam loading compensation and Power Unbalance Compensation Loop for RF amplifiers Combination.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2017-THPAB134

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPAB135

Digital LLRF for MAX IV

cavity, LLRF, FPGA, vacuum

4037

A. Salom, F. Pérez
ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain
Å. Andersson, R. Lindvall, L. Malmgren, A.M. Milan, A.M. Mitrovic
MAX IV Laboratory, Lund University, Lund, Sweden

The MAX IV facility consists of a 3 GeV Storage Ring(SR), a 1.5 GeV SR, and a linear accelerator (fed by two guns) that serves as a full-energy injector to the rings, but also as a driver for the Short Pulse Facility. The RF systems of the two SRs work at 100MHz. There are 6 normal conducting capacity loaded accelerating cavities and three Landau passive cavities in the 3GeV SR. In the 1.5GeV SR there are two accelerating cavities and two Landau cavities with the same characteristics. Each of these cavities is fed by a modular 60kW SSA. In the 3 GeV SR the power will be doubled by adding a second SSA when required. A digital Low Level RF system has been developed using commercial uTCA boards, with a Virtex-6 FPGA mother board (Perseus 601X) and two double stack FMC boards with fast ADCs and DACs. The large capabilities of state-of-the-art FPGAs allowed including the control of two normal conducing cavities and two landau cavities in one single LLRF system, reducing the development costs. Other utilities like the handling of fast interlocks and post-mortem analysis were also added to this system. This paper summarizes the main capabilities and performance of this DLLRF.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2017-THPAB135

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)