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| FOAB01 |
Imaging System Integration at the SNS
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714 |
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- W. Blokland, K. C. Goetz, T. A. Pelaia, T. J. Shea
ORNL, Oak Ridge, Tennessee
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Over the past several years, a variety of imaging systems have been deployed at Oak Ridge National Laboratory's (ORNL's) Spallation Neutron Source (SNS). The systems have supported accelerator instrumentation, neutron beam measurement, target commissioning, and laser diagnostics. For each application, performance requirements drove the choice of camera technology, and this naturally led to a variety of interfaces. This paper will describe the experience gained during the integration and operation of these systems. Several challenges will be highlighted, including algorithms for quantitative measurements, correlation with other accelerator data, real-time video distribution, and storage of large data sets. Although heterogeneous systems must continue to be deployed to meet imaging needs, some common tools and technologies have been identified and are expected to enhance system integration efforts.
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| FOAB02 |
Digital Phase Control System for SSRF Linac
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717 |
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- D. K. Liu, L. Y. Yu, C. X. Yin
SINAP, Shanghai
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SSRF 150MeV linac includes two klystrons and two solid power amplifers, which drive two klystrons, respectively. The accelerating section is constant gradient accelerating structure, and its working frequency is 2998MHz, six times the storage ring RF frequency. In order to reach the requirement for the RF phase stability (±1 degree), the full digital phase control system, which includes RF front-end, AD, DA, and FPGA, is designed. FPGA, the key for phase control system, contains digital I/Q demoulator (phase detector), digital I/Q modulator (phase shifter), and control algorithms. Klystron forward signal is down converted to IF (12.5MHz), which is detected by ADC with 50MHz clock. Digital I/Q is generated by ADC sampling data and then sent to control algorithms in FPGA. After processed by control algorithms, digital I/Q is converted to IF by DAC (50MHz). IF signal from DAC output is up converted to RF and sent to solid RF power amplifer. With the aid of FPGA, the whole period of closed-loop is about 80ns, and delay of closed-loop is less than 600ns. The test results of digital phase control system are presented in this paper.
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| FOAB03 |
Ethernet Based Embedded IOC for FEL Control Systems
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720 |
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- A. C. Grippo, K. Jordan, S. W. Moore, D. W. Sexton, J. Yan
Jefferson Lab, Newport News, Virginia
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An Ethernet-based embedded Input Output Controller (IOC) has been developed as part of an upgrade to the control system for the Free Electron Laser Project at Jefferson Lab. Currently most of the FEL systems are controlled, configured, and monitored using a central VME bus-based configuration. These crate-based systems are limited in growth and usually interleave multiple systems. In order to accommodate incremental system growth and lower channel costs, we developed a standalone system, an Ethernet-based embedded controller called the Single Board IOC (SBIOC). The SBIOC is a module that integrates an Altera FPGA and the Arcturus uCdimm Coldfire 5282 Microcontroller daughter card into one module, which can be easily configured for different kinds of I/O devices. The microcontroller is a complete System-on-Module, including highly integrated functional blocks. A real-time operating system, RTEMS, is cross-compiled with EPICS, allowing us to download the RTEMS kernel, IOC device supports, and databases into the microcontroller. This embedded IOC system has the features of a low-cost IOC, free open source RTOS, plug-and-play-like ease of installation, and flexibility.
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