Keyword: Ethernet
Paper Title Other Keywords Page
WEPAB298 Design of an Accurate LLRF System for an Array of Two-Gap Resonators controls, LLRF, FPGA, distributed 3360
 
  • D.A. Liakin, S.V. Barabin, T. Kulevoy, A.Y. Orlov
    ITEP, Moscow, Russia
 
  A particle accelerator based on an array of two-gap resonators requires a control system, which is responsible for precise setup and stabilization of the phase and magnitude of the electromagnetic field in resonators. We develop a cost-effective LLRF system for the array of more than 80 resonators and three different operating frequencies. The design is based on proved solution used for 5-resonators accelerator HILAC (project NICA, Dubna). This paper gives an overview of the basic structure and some specific features of the developing LLRF control system.  
poster icon Poster WEPAB298 [0.355 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2021-WEPAB298  
About • paper received ※ 18 May 2021       paper accepted ※ 23 June 2021       issue date ※ 30 August 2021  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)  
 
WEPAB310 Study and Design of a High-Performance Computing Infrastructure for Iranian Light Source Facility Based on the Accelerator Physicists and Engineers’ Applications Requirements software, network, hardware, simulation 3402
 
  • K. Mahmoudi, H. Haedar, A. Khaleghi
    IKIU, Qazvin, Iran
  • M. Akbari, A. Khaleghi
    ILSF, Tehran, Iran
  • S. Mahmoudi
    IUST, Narmac, Tehran, Iran
 
  Synchrotron design and operation are one of the complex tasks which requires a lot of precise computation. As an example, we could mention the simulations done for calculating the impedance budget of the machine which requires a notable amount of computational power. In this paper we are going to review different HPC scenarios suitable for this matter then we will present our design of a suitable HPC based on the accelerator physicists and engineers’ needs. Going through different HPC scenarios such as shared memory architectures, distributed memory architectures, cluster, grid and cloud computing we conclude implementation of a dedicated computing cluster can be desired for ILSF. Cluster computing provides the opportunity for easy and saleable scientific computation for ILSF also another advantage is that its resources can be used for running cloud or grid computing platforms as well.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2021-WEPAB310  
About • paper received ※ 19 May 2021       paper accepted ※ 19 July 2021       issue date ※ 12 August 2021  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)  
 
THPAB287 Providing Computing Power for High Level Controllers in MicroTCA-based LLRF Systems via PCI Express Extension controls, LLRF, software, cavity 4363
 
  • P. Nonn, A. Eichler, S. Pfeiffer, H. Schlarb, J.H.K. Timm
    DESY, Hamburg, Germany
 
  It is possible to connect the PCIe bus of a high performance computer to a MicroTCA crate. This allows the software on the computer to communicate with the modules in the crate, as if they were peripherals of the computer. This article will discuss the use of this feature in respect to accelerator control with a focus on High Level Controllers.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2021-THPAB287  
About • paper received ※ 19 May 2021       paper accepted ※ 26 July 2021       issue date ※ 16 August 2021  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)