ICALEPCS2021 - List of Authors (Bielawski, B.)

Paper	Title	Page
THPV033	Reusable Real-Time Software Components for the SPS Low Level RF Control System	939
	M. Sumiński, K. Adrianek, B. Bielawski, A.C. Butterworth, J. Egli, G. Hagmann, P. Kuzmanović, S. Novel González, A. Rey, A. Spierer CERN, Geneva, Switzerland
	In 2021 the Super Proton Synchrotron has been recommissioned after a complete renovation of its low level RF system (LLRF). The new system has largely moved to digital signal processing implemented as a set of functional blocks (IP cores) in Field Programmable Gate Arrays (FPGAs) with associated software to control them. Some of these IP cores provide generic functionalities such as timing, function generation, data resampling and signal acquisition, and are reused in several components, with a potential application in other accelerators. To take full advantage of the modular approach, IP core flexibility must be complemented by the software stack. In this paper we present steps we have taken to reach this goal from the software point of view, and describe the custom tools and procedures used to implement the various software layers.
	Poster THPV033 [1.234 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THPV033
About •	Received ※ 09 October 2021 Accepted ※ 25 February 2022 Issue date ※ 28 February 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Reusable Real-Time Software Components for the SPS Low Level RF Control System

939

M. Sumiński, K. Adrianek, B. Bielawski, A.C. Butterworth, J. Egli, G. Hagmann, P. Kuzmanović, S. Novel González, A. Rey, A. Spierer
CERN, Geneva, Switzerland

In 2021 the Super Proton Synchrotron has been recommissioned after a complete renovation of its low level RF system (LLRF). The new system has largely moved to digital signal processing implemented as a set of functional blocks (IP cores) in Field Programmable Gate Arrays (FPGAs) with associated software to control them. Some of these IP cores provide generic functionalities such as timing, function generation, data resampling and signal acquisition, and are reused in several components, with a potential application in other accelerators. To take full advantage of the modular approach, IP core flexibility must be complemented by the software stack. In this paper we present steps we have taken to reach this goal from the software point of view, and describe the custom tools and procedures used to implement the various software layers.

Poster THPV033 [1.234 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2021-THPV033

About •

Received ※ 09 October 2021 Accepted ※ 25 February 2022 Issue date ※ 28 February 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)