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Nakagawa, H.

Paper Title Page
TOAB02 Current Status of the Control System for J-PARC Accelerator Complex 62
  • M. Adachi, S. F. Fukuta, S. H. Hatakeyama, M. T. Tanaka
    MELCO SC, Tsukuba
  • A. Akiyama, N. Kamikubota, T. Katoh, K. Kudo, T. Matsumoto, H. Nakagawa, J.-I. Odagiri, Y. Takeuchi, N. Yamamoto
    KEK, Ibaraki
  • H. Ikeda, T. Suzuki, N. T. Tsuchiya
    JAEA, Ibaraki-ken
  • Y. I. Itoh, Y. Kato, M. Kawase, H. Sakaki, H. Sako, G. B. Shen, H. Takahashi
    JAEA/J-PARC, Tokai-Mura, Naka-Gun, Ibaraki-Ken
  • S. Motohashi, M. Takagi, S. Y. Yoshida
    Kanto Information Service (KIS), Accelerator Group, Ibaraki
  • S. S. Sawa
    Total Support Systems Corporation, Tokai-mura, Naka-gun, Ibaraki
  • M. S. Sugimoto
    Mitsubishi Electric Control Software Corp, Kobe
  • H. Yoshikawa
    KEK/JAEA, Ibaraki-Ken
  J-PARC accelerator complex consists of a proton linac (LINAC), > a Rapid Cycle Synchrotron (RCS), and a Main Ring synchrotron (MR). The commissioning of LINAC already started in November 2006, while the commissioning of Main Ring synchrotron (MR) is scheduled in May 2008. Most of the machine components of MR have been installed in the tunnel. Introduction of electronic modules and wiring will be made by the end of 2007. For the control of MR, the J-PARC accelerator control network was extended to include the MR related parts in March 2007. IOC computers (VME-bus computers) for MR will be introduced in 2007. In addition, more server computers for application development will be also introduced in 2007. This paper reports the status of development for the J-PARC MR control system.  
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WPPA33 Console System Using Thin Client for the J-PARC Accelerator 383
  • T. Iitsuka, S. Motohashi, M. Takagi, S. Y. Yoshida
    Kanto Information Service (KIS), Accelerator Group, Ibaraki
  • N. Kamikubota, T. Katoh, H. Nakagawa, J.-I. Odagiri, N. Yamamoto
    KEK, Ibaraki
  An accelerator console system, based on a commercial thin client, has been developed for J-PARC accelerator operation and software development. Using thin client terminals, we expect a higher reliability and longer life-cycle due to more robust hardware (i.e., diskless and fanless configuration) than standard PCs. All of the console terminals share a common development/operation environment. We introduced LDAP (Lightweight Directory Access Protocol) for user authentication and NFS (Network File System) to provide users with standard tools and environment (EPICS tools, Java SDK, and so on) with standard directory structures. We have used the console system for beam commissioning and software development in the J-PARC. This paper describes early experiences with them.  
WPPB14 Development of a Signal Processing Board for Spill Digital Servo System for Proton Synchrotron 430
  • T. Adachi, R. Muto, H. Sato, H. Someya, M. Tomizawa, H. Nakagawa
    KEK, Ibaraki
  • T. I. Ichikawa, K. Mochiki
    Musasi Institute of Technology, Instrumentation and Control Laboratory, Tokyo
  • A. Kiyomichi
    JAEA/J-PARC, Tokai-Mura, Naka-Gun, Ibaraki-Ken
  • K. Noda
    NIRS, Chiba-shi
  A prototype data processing board for a digital spill control system has been made. The system is considered to be used to control proton beams in 50-GeV synchrotron rings of J-PARC. The prototype circuit board consists of four ADCs, two FPGAs, a DSP, memories, and four DACs. The four inputs of the processing board are assumed to be an intensity signal of the proton beam in the accelerator rings, a digital gate signal that indicates the duration of beam extraction, a spill signal that shows the intensity of the extracted proton beam, and a reserved signal. The resolution and maximum sampling speed of the ADC are 16 bit and 2.5 Msps, respectively. One of the FPGAs is Vartex-2 1000-4C, and a real-time power spectrum analyzer will be implemented. It analyzes the spill signal every 1ms or shorter period. The analyzed result reflects optimum parameters used in spill control by servo. The DSP takes charge of these digital servo processing. The DACs with 16-bit resolution drive control signals for magnet currents. The system has another FPGA for communication between the processing board and network. MicroBlase CPU core is implemented, and uCLinux is installed to use EPICS.