2011 Particle Accelerator Conference - List of Keywords (low-level-rf)

Paper	Title	Other Keywords	Page
MOP196	A Modular Architecture for Accelerator Instrumentation	controls, feedback, instrumentation, target	459
	J.H. DeLong BNL, Upton, Long Island, New York, USA
	Funding: US Department of Energy With accelerated schedules and finite resources the development of a common open source platform for accelerator instrumentation is required. This effort has led to the development of a flexible architecture with clearly defined interfaces. The resulting platform is currently used to implement fast orbit feedback as well as the Beam Position monitors for NSLS-II. The design includes an embedded processor, digital signal processing resources and communications interfaces to controls, the timing system and other devices distributed throughout the accelerator complex. This new architecture promotes customization and design re-use and is presented as an Open Source Hardware development project.

MOP296	Embedded System Architecture and Capabilities of the RHIC LLRF Platform	controls, LLRF, feedback, monitoring	672
	F. Severino, M. Harvey, T. Hayes, L.T. Hoff, R.C. Lee, A. Marusic, P. Oddo, K.S. Smith, K.L. Unger BNL, Upton, Long Island, New York, USA
	Funding: Work supported by Brookhaven Science Associates, LLC under Contract No. DE-AC02-98CH10886 with the U.S. Department of Energy. A high performance FPGA based platform has been developed for the RHIC Low Level RF system upgrade, and is now replacing our aging VME based systems. This new platform employs a sophisticated embedded architecture to implement its core functionality. This architecture provides a control system interface, manages remote access to all configuration parameters and diagnostic data, supports communication between all system components, enables real time application specific processing, monitors system health, etc. This paper will describe the embedded architecture and its capabilities, with emphasis on its application at RHIC.

WEOBN4	Multipurpose Controller Based on a FPGA with EPICS Integration	controls, EPICS, monitoring, LLRF	1407
	P. Echevarria, I. Arredondo, N. Garmendia, H. Hassanzadegan, L. Muguira ESS Bilbao, Bilbao, Spain D. Belver, M. del Campo ESS-Bilbao, Zamudio, Spain V. Etxebarria, J. Jugo University of the Basque Country, Faculty of Science and Technology, Bilbao, Spain
	In this work a multipurpose configurable control system is presented. This controller is based on a high performance FPGA for a fast control connected to a Host PC which works as an EPICS server to allow a remote control. The communication between both parts is made by a register bank implemented in the FPGA and which is accessible by the Host PC by means of a Compact PCI bus. The initialization values, the numeric representation of the digital signals and the EPICS database are configured by an XML file. This control scheme has been prototyped for two applications: Low Level RF and Beam Position Monitoring. The former contains three digital loops to control the amplitude and phase of the RF supply and the geometry of the cavity. The latter processes the information from four capacitive buttons to calculate the position of the beam. In both systems, the necessary parameters for the digital processing of the acquired signals (using fast ADCs) and intermediate calculations are stored in the register bank connected to the cPCI bus. These systems are being developed for the ESS-Bilbao facility which will be built in Bilbao, Spain.
	Slides WEOBN4 [0.621 MB]

Paper

Title

Other Keywords

Page

MOP196

A Modular Architecture for Accelerator Instrumentation

controls, feedback, instrumentation, target

459

J.H. DeLong
BNL, Upton, Long Island, New York, USA

Funding: US Department of Energy
With accelerated schedules and finite resources the development of a common open source platform for accelerator instrumentation is required. This effort has led to the development of a flexible architecture with clearly defined interfaces. The resulting platform is currently used to implement fast orbit feedback as well as the Beam Position monitors for NSLS-II. The design includes an embedded processor, digital signal processing resources and communications interfaces to controls, the timing system and other devices distributed throughout the accelerator complex. This new architecture promotes customization and design re-use and is presented as an Open Source Hardware development project.

MOP296

Embedded System Architecture and Capabilities of the RHIC LLRF Platform

controls, LLRF, feedback, monitoring

672

F. Severino, M. Harvey, T. Hayes, L.T. Hoff, R.C. Lee, A. Marusic, P. Oddo, K.S. Smith, K.L. Unger
BNL, Upton, Long Island, New York, USA

Funding: Work supported by Brookhaven Science Associates, LLC under Contract No. DE-AC02-98CH10886 with the U.S. Department of Energy.
A high performance FPGA based platform has been developed for the RHIC Low Level RF system upgrade, and is now replacing our aging VME based systems. This new platform employs a sophisticated embedded architecture to implement its core functionality. This architecture provides a control system interface, manages remote access to all configuration parameters and diagnostic data, supports communication between all system components, enables real time application specific processing, monitors system health, etc. This paper will describe the embedded architecture and its capabilities, with emphasis on its application at RHIC.

WEOBN4

Multipurpose Controller Based on a FPGA with EPICS Integration

controls, EPICS, monitoring, LLRF

1407

P. Echevarria, I. Arredondo, N. Garmendia, H. Hassanzadegan, L. Muguira
ESS Bilbao, Bilbao, Spain
D. Belver, M. del Campo
ESS-Bilbao, Zamudio, Spain
V. Etxebarria, J. Jugo
University of the Basque Country, Faculty of Science and Technology, Bilbao, Spain

In this work a multipurpose configurable control system is presented. This controller is based on a high performance FPGA for a fast control connected to a Host PC which works as an EPICS server to allow a remote control. The communication between both parts is made by a register bank implemented in the FPGA and which is accessible by the Host PC by means of a Compact PCI bus. The initialization values, the numeric representation of the digital signals and the EPICS database are configured by an XML file. This control scheme has been prototyped for two applications: Low Level RF and Beam Position Monitoring. The former contains three digital loops to control the amplitude and phase of the RF supply and the geometry of the cavity. The latter processes the information from four capacitive buttons to calculate the position of the beam. In both systems, the necessary parameters for the digital processing of the acquired signals (using fast ADCs) and intermediate calculations are stored in the register bank connected to the cPCI bus. These systems are being developed for the ESS-Bilbao facility which will be built in Bilbao, Spain.

Slides WEOBN4 [0.621 MB]