ICALEPCS2017 - List of Authors (D'Ewart, J.M.)

Paper	Title	Page
THMPL08	The SLAC Common-Platform Firmware for High-Performance Systems	1286
	T. Straumann, R. Claus, J.M. D'Ewart, J.C. Frisch, G. Haller, R.T. Herbst, B. Hong, U. Legat, L. Ma, J.J. Olsen, B.A. Reese, R. Ruckman, L. Sapozhnikov, S.R. Smith, D. Van Winkle, J.A. Vásquez, M. Weaver, E. Williams, C. Xu, A. Young SLAC, Menlo Park, California, USA
	Funding: Work supported by the US Department of Energy, Office of Science under contract DE-AC02-76SF00515 LCLS-II's high beam rate of almost 1MHz and the requirement that several "high-performance" systems (such as MPS, BPM, LLRF, timing etc.) shall resolve individual bunches precludes the use of a traditional software based control system but requires many core services to be implemented in FPGA logic. SLAC has created a comprehensive open-source firmware framework which implements many commonly used blocks (e.g., timing, globally-synchronized fast data buffers, MPS, diagnostic data capture), libraries (Ethernet protocol stack, AXI interconnect, FIFOs, memory etc.) and interfaces (e.g., for timing, diagnostic data etc.) thus providing a versatile platform on top of which powerful high-performance systems can be built and rapidly integrated.
	Slides THMPL08 [0.579 MB]
	Poster THMPL08 [0.630 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL08
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THPHA020	LCLS-II Undulator Motion Control	1379
	K.R. Lauer, A.D. Alarcon, C.J. Andrews, S. Babel, J.D. Bong, M. Boyes, J.M. D'Ewart, Yu.I. Levashov, D.S. Martinez-Galarce, B.D. McKee, H.-D. Nuhn, M. Petree, M. Rowen, Z.R. Wolf SLAC, Menlo Park, California, USA D. Arbelaez, D. Bianculli, A.P. Brown, J.N. Corlett, A.J. DeMello, L. Garcia Fajardo, J.-Y. Jung, M. Leitner, S. Marks, K.A. McCombs, D.V. Munson, K.L. Ray, D.A. Sadlier, E.J. Wallén LBNL, Berkeley, California, USA G. Janša, Ž. Oven Cosylab, Ljubljana, Slovenia M. Merritt, M.L. Smith, R.J. Voogd, J.Z. Xu ANL, Argonne, Illinois, USA
	Funding: Department of Energy contract DE-AC02-76SF00515. At the heart of the LCLS-II are two undulator lines: the hard x-ray (HXR) line and the soft x-ray line (SXR). The SXR line is comprised of 21 variable gap undulator segments separated by an interspace stands with a cam positioning system capable of positioning in 5 degrees of freedom (DOF). The undulator segment motion control utilizes the Aerotech Ensemble motion controller through an EPICS Soft IOC (input-output controller). Its drive system consists of a Harmonic Drive servo system with feedback from two absolute full-gap encoders. Additional Aerotech motion controllers are used to control the cam-positioning system and phase shifters of the interspace stand. The HXR line is comprised of 32 undulator segments each including an integrated interspace assembly. The segment girder is placed on two stands with a similar cam-positioning system as in the SXR line allowing for movement in 5 DOF. As one of the design goals of the HXR line was to reuse the original LCLS girder positioning system, the motion control system is an upgraded version of that original system, using RTEMS on VME with Animatics SmartMotors.
	Poster THPHA020 [6.055 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA020
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THPHA138	YCPSWASYN: EPICS Driver for FPGA Register Access and Asynchronous Messaging	1707
	J.A. Vásquez, J.M. D'Ewart, K.H. Kim, T. Straumann, E. Williams SLAC, Menlo Park, California, USA
	The Linac Coherent Light Source II (LCLS-II) is a major upgrade of the LCLS facility at SLAC, scheduled to start operations in 2020. The High Performance Systems (HPS) defines a set of LCLS-II controls sub-systems which are directly impacted by its 1 MHz operation. It is formed around a few key concepts: ATCA based packaging, digital and analog application boards, and 10G Ethernet based interconnections for controls. The Common Platform provides the common parts of the HPS in term of hardware, firmware, and software. The Common Platform Software (CPSW) provides a standardized interface to the common platform's FPGA for all high-level software. YAML is used to define the hardware topology and all necessary parameters. YCPSWASYN is an asynPortDriver based EPICS module for FPGA register access and asynchronous messaging using CPSW. YCPSWSYN has two operation modes: an automatic mode where PVs are automatically created for all registers and the record's fields are populated with information found in YAML; and a manual mode where the engineer can choose which register to expose via PVs and freely choose the record's filed information.
	Poster THPHA138 [1.189 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA138
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

The SLAC Common-Platform Firmware for High-Performance Systems

1286

T. Straumann, R. Claus, J.M. D'Ewart, J.C. Frisch, G. Haller, R.T. Herbst, B. Hong, U. Legat, L. Ma, J.J. Olsen, B.A. Reese, R. Ruckman, L. Sapozhnikov, S.R. Smith, D. Van Winkle, J.A. Vásquez, M. Weaver, E. Williams, C. Xu, A. Young
SLAC, Menlo Park, California, USA

Funding: Work supported by the US Department of Energy, Office of Science under contract DE-AC02-76SF00515
LCLS-II's high beam rate of almost 1MHz and the requirement that several "high-performance" systems (such as MPS, BPM, LLRF, timing etc.) shall resolve individual bunches precludes the use of a traditional software based control system but requires many core services to be implemented in FPGA logic. SLAC has created a comprehensive open-source firmware framework which implements many commonly used blocks (e.g., timing, globally-synchronized fast data buffers, MPS, diagnostic data capture), libraries (Ethernet protocol stack, AXI interconnect, FIFOs, memory etc.) and interfaces (e.g., for timing, diagnostic data etc.) thus providing a versatile platform on top of which powerful high-performance systems can be built and rapidly integrated.

Slides THMPL08 [0.579 MB]

Poster THMPL08 [0.630 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL08

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA020

LCLS-II Undulator Motion Control

1379

K.R. Lauer, A.D. Alarcon, C.J. Andrews, S. Babel, J.D. Bong, M. Boyes, J.M. D'Ewart, Yu.I. Levashov, D.S. Martinez-Galarce, B.D. McKee, H.-D. Nuhn, M. Petree, M. Rowen, Z.R. Wolf
SLAC, Menlo Park, California, USA
D. Arbelaez, D. Bianculli, A.P. Brown, J.N. Corlett, A.J. DeMello, L. Garcia Fajardo, J.-Y. Jung, M. Leitner, S. Marks, K.A. McCombs, D.V. Munson, K.L. Ray, D.A. Sadlier, E.J. Wallén
LBNL, Berkeley, California, USA
G. Janša, Ž. Oven
Cosylab, Ljubljana, Slovenia
M. Merritt, M.L. Smith, R.J. Voogd, J.Z. Xu
ANL, Argonne, Illinois, USA

Funding: Department of Energy contract DE-AC02-76SF00515.
At the heart of the LCLS-II are two undulator lines: the hard x-ray (HXR) line and the soft x-ray line (SXR). The SXR line is comprised of 21 variable gap undulator segments separated by an interspace stands with a cam positioning system capable of positioning in 5 degrees of freedom (DOF). The undulator segment motion control utilizes the Aerotech Ensemble motion controller through an EPICS Soft IOC (input-output controller). Its drive system consists of a Harmonic Drive servo system with feedback from two absolute full-gap encoders. Additional Aerotech motion controllers are used to control the cam-positioning system and phase shifters of the interspace stand. The HXR line is comprised of 32 undulator segments each including an integrated interspace assembly. The segment girder is placed on two stands with a similar cam-positioning system as in the SXR line allowing for movement in 5 DOF. As one of the design goals of the HXR line was to reuse the original LCLS girder positioning system, the motion control system is an upgraded version of that original system, using RTEMS on VME with Animatics SmartMotors.

Poster THPHA020 [6.055 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA138

YCPSWASYN: EPICS Driver for FPGA Register Access and Asynchronous Messaging

1707

J.A. Vásquez, J.M. D'Ewart, K.H. Kim, T. Straumann, E. Williams
SLAC, Menlo Park, California, USA

The Linac Coherent Light Source II (LCLS-II) is a major upgrade of the LCLS facility at SLAC, scheduled to start operations in 2020. The High Performance Systems (HPS) defines a set of LCLS-II controls sub-systems which are directly impacted by its 1 MHz operation. It is formed around a few key concepts: ATCA based packaging, digital and analog application boards, and 10G Ethernet based interconnections for controls. The Common Platform provides the common parts of the HPS in term of hardware, firmware, and software. The Common Platform Software (CPSW) provides a standardized interface to the common platform's FPGA for all high-level software. YAML is used to define the hardware topology and all necessary parameters. YCPSWASYN is an asynPortDriver based EPICS module for FPGA register access and asynchronous messaging using CPSW. YCPSWSYN has two operation modes: an automatic mode where PVs are automatically created for all registers and the record's fields are populated with information found in YAML; and a manual mode where the engineer can choose which register to expose via PVs and freely choose the record's filed information.

Poster THPHA138 [1.189 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA138

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)