IBIC2012 - List of Keywords (embedded)

Paper	Title	Other Keywords	Page
TUPA22	Design of RF Front End for Cavity Beam Position Monitor based on ICs	cavity, simulation, FPGA, FEL	383
	B.P. Wang, Z.C. Chen, Y.B. Leng, L.Y. Yu, R.X. Yuan, W.M. Zhou SINAP, Shanghai, People's Republic of China
	RF front end has the significant impact on the performance of cavity beam position monitor (CBPM) which is indispensable beam instrumentation component in free electron laser(FEL) or linear collider facility. With many new advances in data converter and radio technology, complex RF front end design has been greatly simplified. Now based on digital intermediate frequency (IF) receiver architecture, a new RF front end for (CBPM) has been designed and fabricated using surface mount component on print circuit board (PCB). The front end contains analog-digital converter used to digitize the IF signals. The whole system would be integrated to a digital board developed by our lab to produce the dedicated signal processor for CBPM. There is an Xilinx Vertex-5 FPGA device on the digital board and relevant signal processing algorithm has been implemented on it using VHDL. The details about design and test results would be introduced blow.

TUPA31	A Real-Time FPGA Based Algorithm for the Combination of Beam Loss Acquisition Methods used for Measurement Dynamic Range Expansion	FPGA, simulation, monitoring, operation	419
	M. Kwiatkowski, M. Alsdorf, B. Dehning, W. Viganò, C. Zamantzas CERN, Geneva, Switzerland
	The aim of the Beam Loss Monitoring Dual Polarity (BLEDP) module under development at the European Organisation for Nuclear Research (CERN) is to measure and digitise with high precision the current produced by several types of beam loss detectors. The BLEDP module consists of eight analogue channels each with a fully differential integrator and an accompanying 16 bit ADC at the output of each analogue integrator. The on-board FPGA device controls the integral periods, instructs the ADC devices to perform measurements at the end of each period and collects the measurements. In the next stage it combines the number of charge and discharge cycles accounted in the last interval together with the cycle fractions observed using the ADC samples to produce a digitized high precision value of the charges collected. This paper describes briefly the principle of the fully differential integrator and focuses on the algorithm employed to process the digital data.

Paper

Title

Other Keywords

Page

TUPA22

Design of RF Front End for Cavity Beam Position Monitor based on ICs

cavity, simulation, FPGA, FEL

383

B.P. Wang, Z.C. Chen, Y.B. Leng, L.Y. Yu, R.X. Yuan, W.M. Zhou
SINAP, Shanghai, People's Republic of China

RF front end has the significant impact on the performance of cavity beam position monitor (CBPM) which is indispensable beam instrumentation component in free electron laser(FEL) or linear collider facility. With many new advances in data converter and radio technology, complex RF front end design has been greatly simplified. Now based on digital intermediate frequency (IF) receiver architecture, a new RF front end for (CBPM) has been designed and fabricated using surface mount component on print circuit board (PCB). The front end contains analog-digital converter used to digitize the IF signals. The whole system would be integrated to a digital board developed by our lab to produce the dedicated signal processor for CBPM. There is an Xilinx Vertex-5 FPGA device on the digital board and relevant signal processing algorithm has been implemented on it using VHDL. The details about design and test results would be introduced blow.

TUPA31

A Real-Time FPGA Based Algorithm for the Combination of Beam Loss Acquisition Methods used for Measurement Dynamic Range Expansion

FPGA, simulation, monitoring, operation

419

M. Kwiatkowski, M. Alsdorf, B. Dehning, W. Viganò, C. Zamantzas
CERN, Geneva, Switzerland

The aim of the Beam Loss Monitoring Dual Polarity (BLEDP) module under development at the European Organisation for Nuclear Research (CERN) is to measure and digitise with high precision the current produced by several types of beam loss detectors. The BLEDP module consists of eight analogue channels each with a fully differential integrator and an accompanying 16 bit ADC at the output of each analogue integrator. The on-board FPGA device controls the integral periods, instructs the ADC devices to perform measurements at the end of each period and collects the measurements. In the next stage it combines the number of charge and discharge cycles accounted in the last interval together with the cycle fractions observed using the ADC samples to produce a digitized high precision value of the charges collected. This paper describes briefly the principle of the fully differential integrator and focuses on the algorithm employed to process the digital data.