Author: Gore, J.A.
Paper Title Page
WEPD27 Graphical User Interface (GUI) for Testing CAMAC modules 60
 
  • S. Kulkarni, P. V. Bhagwat, J.A. Gore, A.K. Gupta, S. Kailas
    BARC, Mumbai, India
 
  A new program (GUI) for testing CAMAC modules (CAMAC ADC, DAC, Input Gate, Output Register) is developed using Labview and dynamic link libraries (DLLs). On start-up, the program initializes the CAMAC Controller via PCI bus interface, thus enabling communication with CAMAC modules. It can test CAMAC modules through different controls like slider bars, buttons etc. and display status of individual channels with soft panel meters and LEDs. The GUI is extremely useful in troubleshooting hardware problems of CAMAC modules and also in developing new modules.  
poster icon Poster WEPD27 [0.524 MB]  
 
FRCA04 Control System for BARC-TIFR Pelletron 251
 
  • S. Singh, J.A. Gore, S. Kulkarni, P. Singh
    BARC, Mumbai, India
 
  Pelletron is 14 MV tandem Accelerator operating from past 20 years. It was operating on DOS based control system. Its control system software and CAMAC controller hardware has been changed recently. Control system software is is a two layer software namely Scanner and operator console. First layer which runs at equipment interface layer interacts with all CAMAC crates acts a server , known as Scanner. Scanner is developed in LINUX and uses TCP/IP protocol suite for interaction with CAMAC and operator interface. Scanner uses shared memory to store machine's runtime data. Operator console is a Graphics interface software developed by using QT APIs. Operator interface is source code portable between MS windows and LInix.  
slides icon Slides FRCA04 [0.663 MB]  
 
FRCC02 A FPGA Based High Speed Data Acquisition Card 271
 
  • J.A. Gore, P. V. Bhagwat, A. Chatterjee, S. Kailas, S. Kulkarni, K. Mahata, S.K. Pandit, V.V. Parkar, A. Shrivastava
    BARC, Mumbai, India
 
  Funding: Bhabha Atomic Research Centre, Nuclear Physics Division
A FPGA based, high speed,two channel,analog input card with a maximum input sampling rate of 1 Giga samples per second (Gsps)per channel has been designed and tested. The card has got an on-board cPCI interface but has been designed in a way that it can also work as a stand-alone system. The card can function as a platform for developing and evaluating different FPGA based hardware designs. Recently, the card has been used to develop a direct sampling Low Level RF (LLRF) controller for controlling the electromagnetic fields of a prototype heavy ion RFQ. It has also been tested for acquisition of data in nuclear physics experiments. Pulses from surface barrier and silicon strip detectors were acquired at an input sampling rate of 1 Gs/s employing 241Am and Am-Pu sources. The design developed for this makes use of pre-triggering. This paper discusses the functionality, salient design issues and features of the card. Finally the hardware designs of above mentioned applications related to different areas of LLRF control and nuclear pulse acquisition are explained and the results obtained are presented.
 
slides icon Slides FRCC02 [1.431 MB]