Author: Nogiec, J.M.
Paper Title Page
WEPV033 Architecture of a Multi-Channel Data Streaming Device with an FPGA as a Coprocessor 724
  • J.M. Nogiec, P. Thompson
    Fermilab, Batavia, Illinois, USA
  Funding: This work was supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics
The design of a data acquisition system often involves the integration of a Field Programmable Gate Array (FPGA) with analog front-end components to achieve precise timing and control. Reuse of these hardware systems can be difficult since they need to be tightly coupled to the communications interface and timing requirements of the specific ADC used. A hybrid design exploring the use of FPGA as a coprocessor to a traditional CPU in a dataflow architecture is presented. Reduction in the volume of data and gradual transitioning of data processing away from a hard real-time environment are both discussed. Chief design concerns, including data throughput and precise synchronization with external stimuli, are addressed. The discussion is illustrated by the implementation of a multi-channel digital integrator, a device based entirely on commercial off-the-shelf (COTS) equipment.
poster icon Poster WEPV033 [0.489 MB]  
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About • Received ※ 09 October 2021       Accepted ※ 21 November 2021       Issue date ※ 08 December 2021  
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