Author: Kowalski, T.
Paper Title Page
TUPV024
Preliminary Design of LLRF System for Polfel Accelerator  
 
  • J. Szewiński, P.R. Bartoszek, K. Chmielewski, K. Kostrzewa, T. Kowalski, P. Markowski, D. Rybka, M. Sitek, Z. Wojciechowski
    NCBJ, Świerk/Otwock, Poland
 
  PolFEL stands for Polish Free Electron Laser, and it is new facility which will be located in the National Centre for Nuclear Research in Świerk in Poland. PolFEL will be Free Electron Laser based on the 200 MeV linear superconducting electron accelerator made of the TESLA type cavities, targeting VUV, IR and THZ wavelengths. Described accelerator will be able to operate in the pulsed wave (PW) mode, but the main operational mode will be continuous wave (CW). PolFEL will operate in the single cavity regulation mode using solid state amplifiers - one per RF structure. Custom and flexible LLRF system will be needed to achieve goals described above. This contribution will present concept of the LLRF system for PolFEL, proposed technologies and techniques, and results of the first successful closed loop operation, performed in the laboratory with the prototype system and copper cavity.  
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WEPV030
Testing of the RTM Carrier Boards for the ESS Accelerator  
 
  • J. Szewiński, P.R. Bartoszek, K. Chmielewski, K. Kostrzewa, T. Kowalski, P. Markowski, D. Rybka, M. Sitek, Z. Wojciechowski
    NCBJ, Świerk/Otwock, Poland
 
  As a part of Polish in-kind contribution to the European Spallation Source (ESS), National Centre for Nuclear Research has developed low cost AMC board, which is used in the MTCA based ESS LLRF system to support RTM units in the crate. Board due to its primary function has been called ’RTM Carrier’, which may be confusing, because it is an AMC. The low cost board, that by concept shall be simple, without own functionality except providing PCIe access from MTCA backplane to the RTM device, has required significant amount of work to create complete firmware and software to cover all board functionality, which was needed to perform factory acceptance tests (FAT) of the described boards. This contribution will describe structure of the FPGA firmware and software used for the RTM Carrier acceptance testing, including techniques used for testing individual functions and features of the board.  
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