ICALEPCS2011 - Table of Session: WEBHMU (Hardware 2)

Paper

Title

Page

The MicroTCA Acquisition and Processing Back-end for FERMI@Elettra Diagnostics

634

A.O. Borga, R. De Monte, M. Ferianis, G. Gaio, L. Pavlovič, M. Predonzani, F. Rossi
ELETTRA, Basovizza, Italy

Funding: The work was supported in part by the Italian Ministry of University and Research under grants FIRB-RBAP045JF2 and FIRB-RBAP06AWK3
Several diagnostics instruments for the FERMI@Elettra FEL require accurate readout, processing, and control electronics; together with a complete integration within the TANGO control system. A custom developed back-end system, compliant to the PICMG MicroTCA standard, provides a robust platform for accommodating such electronics; including reliable slow control and monitoring infrastructural features. Two types of digitizer AMCs have been developed, manufactured, tested and successfully commissioned in the FERMI facility. The first being a fast (160Msps) and high-resolution (16 bits) Analog to Digital and Digital to Analog (A|D|A) Convert Board, hosting 2 A-D and 2 D-A converters controlled by a large FPGA (Xilinx Virtex-5 SX50T) responsible also for the fast communication interface handling. The latter being an Analog to Digital Only (A|D|O), derived from A|D|A, with an analog front-side stage made of 4 A-D converters. A simple MicroTCA Timing Central Hub (MiTiCH) completes the set of modules necessary for operating the system. Several TANGO servers and panels have been developed and put in operation with the support of the controls group. The overall system's architectures, with different practical application examples, together with the specific AMCs' functionalities, are presented. Impressions on our experience on the field using the novel MicroTCA standard are also discussed.

Slides WEBHMUST01 [2.715 MB]

WEBHMUST02

Solid State Direct Drive RF Linac: Control System

638

T. Kluge, M. Back, U. Hagen, O. Heid, M. Hergt, T.J.S. Hughes, R. Irsigler, J. Sirtl
Siemens AG, Erlangen, Germany
R. Fleck
Siemens AG, Corporate Technology, CT T DE HW 4, Erlangen, Germany
H.-C. Schröder
ASTRUM IT GmbH, Erlangen, Germany

Recently a Solid State Direct Drive ® concept for RF linacs has been introduced [1]. This new approach integrates the RF source, comprised of multiple Silicon Carbide (SiC) solid state Rf-modules [2], directly onto the cavity. Such an approach introduces new challenges for the control of such machines namely the non-linear behavior of the solid state RF-modules and the direct coupling of the RF-modules onto the cavity. In this paper we discuss further results of the experimental program [3,4] to integrate and control 64 RF-modules onto a λ/4 cavity. The next stage of experiments aims on gaining better feed forward control of the system and on detailed system identification. For this purpose a digital control board comprising of a Virtex 6 FPGA, high speed DACs/ADCs and trigger I/O is developed and integrated into the experiment and used to control the system. The design of the board is consequently digital aiming at direct processing of the signals. Power control within the cavity is achieved by an outphasing control of two groups of the RF-modules. This allows a power control without degradation of RF-module efficiency.
[1] Heid O., Hughes T., THPD002, IPAC10, Kyoto, Japan
[2] Irsigler R. et al, 3B-9, PPC11, Chicago IL, USA
[3] Heid O., Hughes T., THP068, LINAC10, Tsukuba, Japan
[4] Heid O., Hughes T., MOPD42, HB2010, Morschach, Switzerland

Slides WEBHMUST02 [1.201 MB]

WEBHMULT03

EtherBone - A Network Layer for the Wishbone SoC Bus

642

M. Kreider, W.W. Terpstra
GSI, Darmstadt, Germany
J.H. Lewis, J. Serrano, T. Włostowski
CERN, Geneva, Switzerland

Today, there are several System on a Chip (SoC) bus systems. Typically, these busses are confined on-chip and rely on higher level components to communicate with the outside world. Taking these systems a step further, we see the possibility of extending the reach of the SoC bus to remote FPGAs or processors. This leads to the idea of the EtherBone (EB) core, which connects a Wishbone (WB) Ver. 4 Bus via a Gigabit Ethernet based network link to remote peripheral devices. EB acts as a transparent interconnect module towards attached WB Bus devices. Address information and data from one or more WB bus cycles is preceded with a descriptive header and encapsulated in a UDP/IP packet. Because of this standard compliance, EB is able to traverse Wide Area Networks and is therefore not bound to a geographic location. Due to the low level nature of the WB bus, EB provides a sound basis for remote hardware tools like a JTAG debugger, In-System-Programmer (ISP), boundary scan interface or logic analyser module. EB was developed in the scope of the WhiteRabbit Timing Project (WR) at CERN and GSI/FAIR, which employs GigaBit Ethernet technology to communicate with memory mapped slave devices. WR will make use of EB as means to issue commands to its timing nodes and control connected accelerator hardware.

Slides WEBHMULT03 [1.547 MB]

WEBHMULT04

Sub-nanosecond Timing System Design and Development for LHAASO Project

646

G.H. Gong, S. Chen, Q. Du, J.M. Li, Y. Liu
Tsinghua University, Beijing, People's Republic of China
H. He
IHEP Beijing, Beijing, People's Republic of China

Funding: National Science Foundation of China (No.11005065)
The Large High Altitude Air Shower Observatory (LHAASO) [1] project is designed to trace galactic cosmic ray sources by approximately 10,000 different types of ground air shower detectors. Reconstruction of cosmic ray arrival directions requires sub-nanosecond time synchronization, a novel design of the LHAASO timing system by means of packet-based frequency distribution and time synchronization over Ethernet is proposed. The White Rabbit Protocol (WR) [2] is applied as the infrastructure of the timing system, which implements a distributed adaptive phase tracking technology based on Synchronous Ethernet to lock all local clocks, and a real time delay calibration method based on the Precision Time Protocol to keep all local time synchronized within a nanosecond. We also demonstrate the development and test status on prototype WR switches and nodes.
[1] Cao Zhen, "A future project at tibet: the large high altitude air shower observatory (LHAASO)", Chinese Phys. C 34 249,2010
[2] P. Moreira, et al, "White Rabbit: Sub-Nanosecond Timing Distribution over Ethernet", ISPCS 2009

Slides WEBHMULT04 [8.775 MB]

WEBHMUIO05

Large-scale Distribution of Femtosecond Timing for Accelerators

J.M. Byrd, L.R. Doolittle
LBNL, Berkeley, California, USA

Distribution of timing signals with femtosecond relative stability has become a critical technology for linac-based free electron lasers (FELs) and linear collider accelerator complexes. The uses for this timing distribution include synchronization of diverse array of remote clients such as mode-locked laser oscillators, beam and x-ray diagnostics systems, and RF systems. I will describe recent progress in the technology of femtosecond timing distribution and locking to remote clients. I will also present concepts of how such systems are extended to multiple channels with an emphasis on applications to FELs.

Slides WEBHMUIO05 [10.704 MB]

Paper	Title	Page
WEBHMUST01	The MicroTCA Acquisition and Processing Back-end for FERMI@Elettra Diagnostics	634
	A.O. Borga, R. De Monte, M. Ferianis, G. Gaio, L. Pavlovič, M. Predonzani, F. Rossi ELETTRA, Basovizza, Italy
	Funding: The work was supported in part by the Italian Ministry of University and Research under grants FIRB-RBAP045JF2 and FIRB-RBAP06AWK3 Several diagnostics instruments for the FERMI@Elettra FEL require accurate readout, processing, and control electronics; together with a complete integration within the TANGO control system. A custom developed back-end system, compliant to the PICMG MicroTCA standard, provides a robust platform for accommodating such electronics; including reliable slow control and monitoring infrastructural features. Two types of digitizer AMCs have been developed, manufactured, tested and successfully commissioned in the FERMI facility. The first being a fast (160Msps) and high-resolution (16 bits) Analog to Digital and Digital to Analog (A\|D\|A) Convert Board, hosting 2 A-D and 2 D-A converters controlled by a large FPGA (Xilinx Virtex-5 SX50T) responsible also for the fast communication interface handling. The latter being an Analog to Digital Only (A\|D\|O), derived from A\|D\|A, with an analog front-side stage made of 4 A-D converters. A simple MicroTCA Timing Central Hub (MiTiCH) completes the set of modules necessary for operating the system. Several TANGO servers and panels have been developed and put in operation with the support of the controls group. The overall system's architectures, with different practical application examples, together with the specific AMCs' functionalities, are presented. Impressions on our experience on the field using the novel MicroTCA standard are also discussed.
	Slides WEBHMUST01 [2.715 MB]

WEBHMUST02	Solid State Direct Drive RF Linac: Control System	638
	T. Kluge, M. Back, U. Hagen, O. Heid, M. Hergt, T.J.S. Hughes, R. Irsigler, J. Sirtl Siemens AG, Erlangen, Germany R. Fleck Siemens AG, Corporate Technology, CT T DE HW 4, Erlangen, Germany H.-C. Schröder ASTRUM IT GmbH, Erlangen, Germany
	Recently a Solid State Direct Drive ® concept for RF linacs has been introduced [1]. This new approach integrates the RF source, comprised of multiple Silicon Carbide (SiC) solid state Rf-modules [2], directly onto the cavity. Such an approach introduces new challenges for the control of such machines namely the non-linear behavior of the solid state RF-modules and the direct coupling of the RF-modules onto the cavity. In this paper we discuss further results of the experimental program [3,4] to integrate and control 64 RF-modules onto a λ/4 cavity. The next stage of experiments aims on gaining better feed forward control of the system and on detailed system identification. For this purpose a digital control board comprising of a Virtex 6 FPGA, high speed DACs/ADCs and trigger I/O is developed and integrated into the experiment and used to control the system. The design of the board is consequently digital aiming at direct processing of the signals. Power control within the cavity is achieved by an outphasing control of two groups of the RF-modules. This allows a power control without degradation of RF-module efficiency. [1] Heid O., Hughes T., THPD002, IPAC10, Kyoto, Japan [2] Irsigler R. et al, 3B-9, PPC11, Chicago IL, USA [3] Heid O., Hughes T., THP068, LINAC10, Tsukuba, Japan [4] Heid O., Hughes T., MOPD42, HB2010, Morschach, Switzerland
	Slides WEBHMUST02 [1.201 MB]

WEBHMULT03	EtherBone - A Network Layer for the Wishbone SoC Bus	642
	M. Kreider, W.W. Terpstra GSI, Darmstadt, Germany J.H. Lewis, J. Serrano, T. Włostowski CERN, Geneva, Switzerland
	Today, there are several System on a Chip (SoC) bus systems. Typically, these busses are confined on-chip and rely on higher level components to communicate with the outside world. Taking these systems a step further, we see the possibility of extending the reach of the SoC bus to remote FPGAs or processors. This leads to the idea of the EtherBone (EB) core, which connects a Wishbone (WB) Ver. 4 Bus via a Gigabit Ethernet based network link to remote peripheral devices. EB acts as a transparent interconnect module towards attached WB Bus devices. Address information and data from one or more WB bus cycles is preceded with a descriptive header and encapsulated in a UDP/IP packet. Because of this standard compliance, EB is able to traverse Wide Area Networks and is therefore not bound to a geographic location. Due to the low level nature of the WB bus, EB provides a sound basis for remote hardware tools like a JTAG debugger, In-System-Programmer (ISP), boundary scan interface or logic analyser module. EB was developed in the scope of the WhiteRabbit Timing Project (WR) at CERN and GSI/FAIR, which employs GigaBit Ethernet technology to communicate with memory mapped slave devices. WR will make use of EB as means to issue commands to its timing nodes and control connected accelerator hardware.
	Slides WEBHMULT03 [1.547 MB]

WEBHMULT04	Sub-nanosecond Timing System Design and Development for LHAASO Project	646
	G.H. Gong, S. Chen, Q. Du, J.M. Li, Y. Liu Tsinghua University, Beijing, People's Republic of China H. He IHEP Beijing, Beijing, People's Republic of China
	Funding: National Science Foundation of China (No.11005065) The Large High Altitude Air Shower Observatory (LHAASO) [1] project is designed to trace galactic cosmic ray sources by approximately 10,000 different types of ground air shower detectors. Reconstruction of cosmic ray arrival directions requires sub-nanosecond time synchronization, a novel design of the LHAASO timing system by means of packet-based frequency distribution and time synchronization over Ethernet is proposed. The White Rabbit Protocol (WR) [2] is applied as the infrastructure of the timing system, which implements a distributed adaptive phase tracking technology based on Synchronous Ethernet to lock all local clocks, and a real time delay calibration method based on the Precision Time Protocol to keep all local time synchronized within a nanosecond. We also demonstrate the development and test status on prototype WR switches and nodes. [1] Cao Zhen, "A future project at tibet: the large high altitude air shower observatory (LHAASO)", Chinese Phys. C 34 249,2010 [2] P. Moreira, et al, "White Rabbit: Sub-Nanosecond Timing Distribution over Ethernet", ISPCS 2009
	Slides WEBHMULT04 [8.775 MB]

WEBHMUIO05	Large-scale Distribution of Femtosecond Timing for Accelerators
	J.M. Byrd, L.R. Doolittle LBNL, Berkeley, California, USA
	Distribution of timing signals with femtosecond relative stability has become a critical technology for linac-based free electron lasers (FELs) and linear collider accelerator complexes. The uses for this timing distribution include synchronization of diverse array of remote clients such as mode-locked laser oscillators, beam and x-ray diagnostics systems, and RF systems. I will describe recent progress in the technology of femtosecond timing distribution and locking to remote clients. I will also present concepts of how such systems are extended to multiple channels with an emphasis on applications to FELs.
	Slides WEBHMUIO05 [10.704 MB]