Author: Kwiatkowski, M.
Paper Title Page
WEMMU010 Dependable Design Flow for Protection Systems using Programmable Logic Devices 706
  • M. Kwiatkowski, B. Todd
    CERN, Geneva, Switzerland
  Programmable Logic Devices (PLD) such as Field Programmable Gate Arrays (FPGA) are becoming more prevalent in protection and safety-related electronic systems. When employing such programmable logic devices, extra care and attention needs to be taken. It is important to be confident that the final synthesis result, used to generate the bit-stream to program the device, meets the design requirements. This paper will describe how to maximize confidence using techniques such as Formal Methods, exhaustive Hardware Description Language (HDL) code simulation and hardware testing. An example will be given for one of the critical function of the Safe Machine Parameters (SMP) system, one of the key systems for the protection of the Large Hadrons Collider (LHC) at CERN. The design flow will be presented where the implementation phase is just one small element of the whole process. Techniques and tools presented can be applied for any PLD based system implementation and verification.  
slides icon Slides WEMMU010 [1.093 MB]  
poster icon Poster WEMMU010 [0.829 MB]