Author: Kwiatkowski, M.
Paper Title Page
WEMMU010 Dependable Design Flow for Protection Systems using Programmable Logic Devices 706
 
  • M. Kwiatkowski, B. Todd
    CERN, Geneva, Switzerland
 
  Pro­grammable Logic De­vices (PLD) such as Field Pro­grammable Gate Ar­rays (FPGA) are be­com­ing more preva­lent in pro­tec­tion and safe­ty-re­lat­ed elec­tron­ic sys­tems. When em­ploy­ing such pro­grammable logic de­vices, extra care and at­ten­tion needs to be taken. It is im­por­tant to be con­fi­dent that the final syn­the­sis re­sult, used to gen­er­ate the bit-stream to pro­gram the de­vice, meets the de­sign re­quire­ments. This paper will de­scribe how to max­i­mize con­fi­dence using tech­niques such as For­mal Meth­ods, ex­haus­tive Hard­ware De­scrip­tion Lan­guage (HDL) code sim­u­la­tion and hard­ware test­ing. An ex­am­ple will be given for one of the crit­i­cal func­tion of the Safe Ma­chine Pa­ram­e­ters (SMP) sys­tem, one of the key sys­tems for the pro­tec­tion of the Large Hadrons Col­lid­er (LHC) at CERN. The de­sign flow will be pre­sent­ed where the im­ple­men­ta­tion phase is just one small el­e­ment of the whole pro­cess. Tech­niques and tools pre­sent­ed can be ap­plied for any PLD based sys­tem im­ple­men­ta­tion and ver­i­fi­ca­tion.  
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