ICALEPCS2011 - List of Authors (Cheblakov, P.B.)

Paper

Title

Page

PCI Hardware Support in LIA-2 Control System

916

D. Bolkhovityanov, P.B. Cheblakov
BINP SB RAS, Novosibirsk, Russia

LIA-2 control system* is built on cPCI crates with x86-compatible processor boards running Linux. Slow electronics is connected via CAN-bus, while fast electronics (4MHz and 200MHz fast ADCs and 200MHz timers) are implemented as cPCI/PMC modules. Several ways to drive PCI control electronics in Linux were examined. Finally a userspace drivers approach was chosen. These drivers communicate with hardware via a small kernel module, which provides access to PCI BARs and to interrupt handling. This module was named USPCI (User-Space PCI access). This approach dramatically simplifies creation of drivers, as opposed to kernel drivers, and provides high reliability (because only a tiny and thoroughly-debugged piece of code runs in kernel). LIA-2 accelerator was successfully commissioned, and the solution chosen has proven adequate and very easy to use. Besides, USPCI turned out to be a handy tool for examination and debugging of PCI devices direct from command-line. In this paper available approaches to work with PCI control hardware in Linux are considered, and USPCI architecture is described.
* "LIA-2 Linear Induction Accelerator Control System", this conference

Poster WEPMN017 [0.954 MB]

WEPMS015

NSLS-II Booster Timing System

1003

P.B. Cheblakov, S.E. Karnaev
BINP SB RAS, Novosibirsk, Russia
J.H. De Long
BNL, Upton, Long Island, New York, USA

The NSLS-II light source includes the main storage ring with beam lines and injection part consisting of 200 MeV linac, 3 GeV booster synchrotron and two transport lines. The booster timing system is a part of NSLS-II timing system which is based on Event Generator (EVG) and Event Receivers (EVRs) fromμResearch Finland. The booster timing is based on the external events coming from NSLS-II EVG: "Pre-Injection", "Injection", "Pre-Extraction", "Extraction". These events are referenced to the specified bunch of the Storage Ring and correspond to the first bunch of the booster. EVRs provide two scales for triggering both of the injection and the extraction pulse devices. The first scale provides triggering of the pulsed septums and the bump magnets in the range of milliseconds and uses TTL outputs of EVR, the second scale provides triggering of the kickers in the range of microseconds and uses CML outputs. EVRs also provide the timing of a booster cycle operation and events for cycle-to-cycle updates of pulsed and ramping parameters, and the booster beam instrumentation synchronization. This paper describes the final design of the booster timing system. The timing system functional and block diagrams are presented.

Poster WEPMS015 [0.799 MB]

WEPMS020

NSLS-II Booster Power Supplies Control

1018

P.B. Cheblakov, S.E. Karnaev, S.S. Serednyakov
BINP SB RAS, Novosibirsk, Russia
W. Louie, Y. Tian
BNL, Upton, Long Island, New York, USA

The NSLS-II booster Power Supplies (PSs) [1] are divided into two groups: ramping PSs providing passage of the beam during the beam ramp in the booster from 200 MeV up to 3 GeV at 300 ms time interval, and pulsed PSs providing beam injection from the linac and extraction to the Storage Ring. A special set of devices was developed at BNL for the NSLS-II magnetic system PSs control: Power Supply Controller (PSC) and Power Supply Interface (PSI). The PSI has one or two precision 18-bit DACs, nine channels of ADC for each DAC and digital input/outputs. It is capable of detecting the status change sequence of digital inputs with 10 ns resolution. The PSI is placed close to current regulators and is connected to the PSC via fiber-optic 50 Mbps data link. The PSC communicates with EPICS IOC through a 100 Mbps Ethernet port. The main function of IOC includes ramp curve upload, ADC waveform data download, and various process variable control. The 256 Mb DDR2 memory on PSC provides large storage for up to 16 ramping tables for the both DACs, and 20 second waveform recorder for all the ADC channels. The 100 Mbps Ethernet port enables real time display for 4 ADC waveforms. This paper describes a project of the NSLS-II booster PSs control. Characteristic features of the ramping magnets control and pulsed magnets control in a double-injection mode of operation are considered in the paper. First results of the control at PS testing stands are presented.
[1] Power Supply Control System of NSLS-II, Y. Tian, W. Louie, J. Ricciardelli, L.R. Dalesio, G. Ganetis, ICALEPCS2009, Japan

Poster WEPMS020 [1.818 MB]

Paper	Title	Page
WEPMN017	PCI Hardware Support in LIA-2 Control System	916
	D. Bolkhovityanov, P.B. Cheblakov BINP SB RAS, Novosibirsk, Russia
	LIA-2 control system* is built on cPCI crates with x86-compatible processor boards running Linux. Slow electronics is connected via CAN-bus, while fast electronics (4MHz and 200MHz fast ADCs and 200MHz timers) are implemented as cPCI/PMC modules. Several ways to drive PCI control electronics in Linux were examined. Finally a userspace drivers approach was chosen. These drivers communicate with hardware via a small kernel module, which provides access to PCI BARs and to interrupt handling. This module was named USPCI (User-Space PCI access). This approach dramatically simplifies creation of drivers, as opposed to kernel drivers, and provides high reliability (because only a tiny and thoroughly-debugged piece of code runs in kernel). LIA-2 accelerator was successfully commissioned, and the solution chosen has proven adequate and very easy to use. Besides, USPCI turned out to be a handy tool for examination and debugging of PCI devices direct from command-line. In this paper available approaches to work with PCI control hardware in Linux are considered, and USPCI architecture is described. * "LIA-2 Linear Induction Accelerator Control System", this conference
	Poster WEPMN017 [0.954 MB]

WEPMS015	NSLS-II Booster Timing System	1003
	P.B. Cheblakov, S.E. Karnaev BINP SB RAS, Novosibirsk, Russia J.H. De Long BNL, Upton, Long Island, New York, USA
	The NSLS-II light source includes the main storage ring with beam lines and injection part consisting of 200 MeV linac, 3 GeV booster synchrotron and two transport lines. The booster timing system is a part of NSLS-II timing system which is based on Event Generator (EVG) and Event Receivers (EVRs) fromμResearch Finland. The booster timing is based on the external events coming from NSLS-II EVG: "Pre-Injection", "Injection", "Pre-Extraction", "Extraction". These events are referenced to the specified bunch of the Storage Ring and correspond to the first bunch of the booster. EVRs provide two scales for triggering both of the injection and the extraction pulse devices. The first scale provides triggering of the pulsed septums and the bump magnets in the range of milliseconds and uses TTL outputs of EVR, the second scale provides triggering of the kickers in the range of microseconds and uses CML outputs. EVRs also provide the timing of a booster cycle operation and events for cycle-to-cycle updates of pulsed and ramping parameters, and the booster beam instrumentation synchronization. This paper describes the final design of the booster timing system. The timing system functional and block diagrams are presented.
	Poster WEPMS015 [0.799 MB]

WEPMS020	NSLS-II Booster Power Supplies Control	1018
	P.B. Cheblakov, S.E. Karnaev, S.S. Serednyakov BINP SB RAS, Novosibirsk, Russia W. Louie, Y. Tian BNL, Upton, Long Island, New York, USA
	The NSLS-II booster Power Supplies (PSs) [1] are divided into two groups: ramping PSs providing passage of the beam during the beam ramp in the booster from 200 MeV up to 3 GeV at 300 ms time interval, and pulsed PSs providing beam injection from the linac and extraction to the Storage Ring. A special set of devices was developed at BNL for the NSLS-II magnetic system PSs control: Power Supply Controller (PSC) and Power Supply Interface (PSI). The PSI has one or two precision 18-bit DACs, nine channels of ADC for each DAC and digital input/outputs. It is capable of detecting the status change sequence of digital inputs with 10 ns resolution. The PSI is placed close to current regulators and is connected to the PSC via fiber-optic 50 Mbps data link. The PSC communicates with EPICS IOC through a 100 Mbps Ethernet port. The main function of IOC includes ramp curve upload, ADC waveform data download, and various process variable control. The 256 Mb DDR2 memory on PSC provides large storage for up to 16 ramping tables for the both DACs, and 20 second waveform recorder for all the ADC channels. The 100 Mbps Ethernet port enables real time display for 4 ADC waveforms. This paper describes a project of the NSLS-II booster PSs control. Characteristic features of the ramping magnets control and pulsed magnets control in a double-injection mode of operation are considered in the paper. First results of the control at PS testing stands are presented. [1] Power Supply Control System of NSLS-II, Y. Tian, W. Louie, J. Ricciardelli, L.R. Dalesio, G. Ganetis, ICALEPCS2009, Japan
	Poster WEPMS020 [1.818 MB]