ANL, Argonne, USA
Purdue University, West Lafayette, Indiana, USA
The first prototype superconducting undulator (SCU0) was successfully installed and commissioned at the Advanced Photon Source (APS) and is delivering photons for user science. All the requirements before operating the SCU0 in the storage ring were satisfied during a short but detailed beam commissioning. The cryogenic system performed very well in the presence of the beam. The total beam-induced heat load on the SCU0 agreed well with the predictions, and the SCU0 is protected from excessive heat loads through a combination of orbit control and SCU0 alignment. When powered, the field integral measured with the beam agreed well with the magnet measurements. An induced quench caused very little beam motion, and did not cause loss of the beam. The device was found to quench during unintentional beam dumps, but quench recovery is transparent to storage ring operation. There were no beam chamber vacuum pressure issues and no negative effect observed on the beam. Finally, the SCU0 was operated well beyond its design requirements, and no significant issues were identified. The beam commissioning results are described in this paper.
ANL, Argonne, USA
A real-time feedback double sector controller (RTFB DSC) for the APS Upgrade has been under design for the past year. Using the Xilinx Zynq-7000 All Programmable System on a Chip FPGA residing on the ZC706 board as the base platform, the upgrade path interfaces to the existing accelerator system and modernizes the beam position monitoring and feedback systems. The modernized system increases the RTFB system sample rate from 1.5 kHz to 22.6 kHz. We report the plan for sector-by-sector upgrades that will occur during system shutdowns and allow the upgraded sectors to operate with the existing sectors. The mapping of the RTFB DSC architecture is shown utilizing the targeted FPGA features. These features include the dual ARM CortexTM-A9 processors, multi-port DDR3 memory controllers, gigabit transceivers, and the programming logic interconnect for implementing advanced orbit feedback controller algorithms using floating-point DSP operations. The RTFB DSC FPGA architecture is revealed as well as subsequent progress on the chassis implementation.