IPAC2015 - List of Authors (Yang, Y.)

Paper	Title	Page
MOPTY008	Preliminary Hardware Implementation of Compensation Mechanism of Superconducting Cavity Failure in C-ADS Linac	953
	Z. Xue, J.P. Dai IHEP, Beijing, People's Republic of China L. Cheng, Y. Yang SINANO, Suzhou, People's Republic of China
	For the proton linear accelerators used in applications such as ADS, due to the nature of the operation, it is essential to have beam failures at the rate several orders of magnitude lower than usual performance of similar accelerators. In order to achieve this extremely high performance reliability requirement, in addition to hardware improvement, a failure tolerant design is mandatory. A compensation mechanism to cope with hardware failure, mainly RF failures of superconducting cavities, will be in place in order to maintain the high uptime, short recovery time and extremely low frequency of beam loss. The hardware implementation of the mechanism poses high challenges due to the extremely tight timing constraints, high logic complexity, and mostly important, high flexibility and short turnaround time due to varying operation contexts. We will explore the hardware implementation of the scheme using fast electronic devices and Field Programmable Gate Array (FPGA). In order to achieve the goals of short recovery time and flexibility in compensation algorithms, an advanced hardware design methodology including high-level synthesis will be used.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2015-MOPTY008
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Paper

Title

Page

Preliminary Hardware Implementation of Compensation Mechanism of Superconducting Cavity Failure in C-ADS Linac

953

Z. Xue, J.P. Dai
IHEP, Beijing, People's Republic of China
L. Cheng, Y. Yang
SINANO, Suzhou, People's Republic of China

For the proton linear accelerators used in applications such as ADS, due to the nature of the operation, it is essential to have beam failures at the rate several orders of magnitude lower than usual performance of similar accelerators. In order to achieve this extremely high performance reliability requirement, in addition to hardware improvement, a failure tolerant design is mandatory. A compensation mechanism to cope with hardware failure, mainly RF failures of superconducting cavities, will be in place in order to maintain the high uptime, short recovery time and extremely low frequency of beam loss. The hardware implementation of the mechanism poses high challenges due to the extremely tight timing constraints, high logic complexity, and mostly important, high flexibility and short turnaround time due to varying operation contexts. We will explore the hardware implementation of the scheme using fast electronic devices and Field Programmable Gate Array (FPGA). In order to achieve the goals of short recovery time and flexibility in compensation algorithms, an advanced hardware design methodology including high-level synthesis will be used.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2015-MOPTY008

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)