IPAC2012 - List of Keywords (low-level-rf)

Paper	Title	Other Keywords	Page
WEPPC001	Input Power Coupler for the IFMIF SRF Linac	cryomodule, vacuum, SRF, controls	2200
	H. Jenhani, P. Bosland, P. Carbonnier, N. Grouas, P. Hardy, V.M. Hennion, F. Orsini, J. Plouin, B. Renard CEA/IRFU, Gif-sur-Yvette, France S.J. Einarson, T.A. Treado CPI, Beverley, Massachusetts, USA
	The design phase of the IFMIF-EVEDA Power Couplers for the Superconductive HWR has been accomplished. TiN and copper coatings specifications have been validated on samples. A coupler window equipped with a truncated antenna and RF matching transition have been fabricated and tested to qualify the manufacturing processes and to demonstrate the technical feasibility of the coupler. Series of tests were successfully performed on these subassemblies. The last part of the design phase consists of the design validation by manufacturing two coupler prototypes and testing their performances at full power. Finishing processes and validation tests are on-going.

THPPC060	Commissioning of the First Klystron-based X-band Power Source at CERN	klystron, vacuum, controls, high-voltage	3428
	J.W. Kovermann, N. Catalan-Lasheras, S. Curt, S. Döbert, G. McMonagle, S.F. Rey, G. Riddone, K.M. Schirm, I. Syratchev, L. Timeo CERN, Geneva, Switzerland J.P. Eichner, A.A. Haase, D.W. Sprehn SLAC, Menlo Park, California, USA A. Hamdi, F. Peauger CEA/DSM/IRFU, France
	A new klystron based x-band rf power source working at 11.994GHz has been installed and commissioned at CERN in collaboration with CEA Saclay and SLAC for CLIC accelerating structure tests. The system comprises a solid state high voltage modulator, an XL5 klystron developed by SLAC, a cavity based SLED type pulse compressor, the necessary low level rf system including rf diagnostics and interlocks and the surrounding vacuum, cooling and controls infrastructure. The klystron can produce up to 50MW rf pulses of 1500ns pulse width and 50Hz repetition rate. After pulse compression, up to 100MW of rf power at 250ns pulse with are available in the structure test bunker. This paper describes in more detail this setup and the results of the commissioning which was necessary to arrive at the mentioned performance.

THPPC075	Development of a Digital Low-level RF Control System for the p-Linac Test Stand at FAIR	controls, linac, cavity, proton	3461
	M. Konrad, U. Bonnes, C. Burandt, R. Eichhorn, J. Enders, P.N. Nonn, N. Pietralla TU Darmstadt, Darmstadt, Germany
	Funding: Work supported by DFG through CRC 634 and by the BMBF under 06 DA 9024 I A test stand for a proton Linac is currently built at GSI in the context of the FAIR project. Its low-level RF control system will be based on a system that has been developed for the S-DALINAC at TU Darmstadt operating at 3 GHz. This system converts the RF signal coming from the cavity down to the base band using a hardware I/Q demodulator. The base-band signals are digitized by ADCs and fed into an FPGA. A custom CPU implemented in the FPGA executes the control algorithm. The resulting signals are I/Q modulated before they are sent back to the cavity. The RF module has to be adapted to the p-LINAC's operating frequency of 325 MHz. Moreover, the p-LINAC will run in pulsed operation whereas the S-DALINAC is operated in CW mode. Different quality factors of the cavities and the pulsed operation require a redesign of the control algorithm. We will report on the modifications necessary to adapt the S-DALINAC's control system to the p-LINAC test stand and on first results obtained from tests with a prototype.

THPPC087	Software Firmware Infrastructure for LLRF4 Based System	LLRF, controls, EPICS, status	3485
	G. Huang, L.R. Doolittle, C. Serrano LBNL, Berkeley, California, USA
	LLRF4 is a successfully designed FPGA based low noise llrf signal process board. The board has been used in server accelerator as low level RF control and timing system. The complexity of maintain and support different version of software and firmware increase as the application increase. This paper describe our attempt to abstract the software and firmware layer. In the software side, the infrastructure support original rgui like GUI and also provide EPICS IOC driver. From the firmware side, the infrastructure separate board hardware dependent driver, the common algorithm implementation and project specific DSP, it also reserved the capability to expend to UDP based communication and next generation llrf board.

THPPC089	LLRF Control for SPX @ APS Demonstration Experiment	cavity, LLRF, controls, resonance	3491
	G. Huang, J.M. Byrd, K. Campbell, L.R. Doolittle, J.B. Greer LBNL, Berkeley, California, USA N.D. Arnold, T.G. Berenc, F. Lenkszus, H. Ma ANL, Argonne, USA
	The SPX experiment at APS is part of the APS upgrade project, using two deflecting cavity to chirp the electron pulse and then generate short pulse x-ray. To minimize the influence to other users on the storage ring, the phase synchronization of the two deflecting cavity are required to be better then 77 femto-second. A LLRF4 board based system is designed to demonstrate the capability of meeting this requirement. This paper discuss the hardware and firmware design of the demo experiment including the cavity emulator, frequency reference generation and LLRF control algorithm.

Paper

Title

Other Keywords

Page

WEPPC001

Input Power Coupler for the IFMIF SRF Linac

cryomodule, vacuum, SRF, controls

2200

H. Jenhani, P. Bosland, P. Carbonnier, N. Grouas, P. Hardy, V.M. Hennion, F. Orsini, J. Plouin, B. Renard
CEA/IRFU, Gif-sur-Yvette, France
S.J. Einarson, T.A. Treado
CPI, Beverley, Massachusetts, USA

The design phase of the IFMIF-EVEDA Power Couplers for the Superconductive HWR has been accomplished. TiN and copper coatings specifications have been validated on samples. A coupler window equipped with a truncated antenna and RF matching transition have been fabricated and tested to qualify the manufacturing processes and to demonstrate the technical feasibility of the coupler. Series of tests were successfully performed on these subassemblies. The last part of the design phase consists of the design validation by manufacturing two coupler prototypes and testing their performances at full power. Finishing processes and validation tests are on-going.

THPPC060

Commissioning of the First Klystron-based X-band Power Source at CERN

klystron, vacuum, controls, high-voltage

3428

J.W. Kovermann, N. Catalan-Lasheras, S. Curt, S. Döbert, G. McMonagle, S.F. Rey, G. Riddone, K.M. Schirm, I. Syratchev, L. Timeo
CERN, Geneva, Switzerland
J.P. Eichner, A.A. Haase, D.W. Sprehn
SLAC, Menlo Park, California, USA
A. Hamdi, F. Peauger
CEA/DSM/IRFU, France

A new klystron based x-band rf power source working at 11.994GHz has been installed and commissioned at CERN in collaboration with CEA Saclay and SLAC for CLIC accelerating structure tests. The system comprises a solid state high voltage modulator, an XL5 klystron developed by SLAC, a cavity based SLED type pulse compressor, the necessary low level rf system including rf diagnostics and interlocks and the surrounding vacuum, cooling and controls infrastructure. The klystron can produce up to 50MW rf pulses of 1500ns pulse width and 50Hz repetition rate. After pulse compression, up to 100MW of rf power at 250ns pulse with are available in the structure test bunker. This paper describes in more detail this setup and the results of the commissioning which was necessary to arrive at the mentioned performance.

THPPC075

Development of a Digital Low-level RF Control System for the p-Linac Test Stand at FAIR

controls, linac, cavity, proton

3461

M. Konrad, U. Bonnes, C. Burandt, R. Eichhorn, J. Enders, P.N. Nonn, N. Pietralla
TU Darmstadt, Darmstadt, Germany

Funding: Work supported by DFG through CRC 634 and by the BMBF under 06 DA 9024 I
A test stand for a proton Linac is currently built at GSI in the context of the FAIR project. Its low-level RF control system will be based on a system that has been developed for the S-DALINAC at TU Darmstadt operating at 3 GHz. This system converts the RF signal coming from the cavity down to the base band using a hardware I/Q demodulator. The base-band signals are digitized by ADCs and fed into an FPGA. A custom CPU implemented in the FPGA executes the control algorithm. The resulting signals are I/Q modulated before they are sent back to the cavity. The RF module has to be adapted to the p-LINAC's operating frequency of 325 MHz. Moreover, the p-LINAC will run in pulsed operation whereas the S-DALINAC is operated in CW mode. Different quality factors of the cavities and the pulsed operation require a redesign of the control algorithm. We will report on the modifications necessary to adapt the S-DALINAC's control system to the p-LINAC test stand and on first results obtained from tests with a prototype.

THPPC087

Software Firmware Infrastructure for LLRF4 Based System

LLRF, controls, EPICS, status

3485

G. Huang, L.R. Doolittle, C. Serrano
LBNL, Berkeley, California, USA

LLRF4 is a successfully designed FPGA based low noise llrf signal process board. The board has been used in server accelerator as low level RF control and timing system. The complexity of maintain and support different version of software and firmware increase as the application increase. This paper describe our attempt to abstract the software and firmware layer. In the software side, the infrastructure support original rgui like GUI and also provide EPICS IOC driver. From the firmware side, the infrastructure separate board hardware dependent driver, the common algorithm implementation and project specific DSP, it also reserved the capability to expend to UDP based communication and next generation llrf board.

THPPC089

LLRF Control for SPX @ APS Demonstration Experiment

cavity, LLRF, controls, resonance

3491

G. Huang, J.M. Byrd, K. Campbell, L.R. Doolittle, J.B. Greer
LBNL, Berkeley, California, USA
N.D. Arnold, T.G. Berenc, F. Lenkszus, H. Ma
ANL, Argonne, USA

The SPX experiment at APS is part of the APS upgrade project, using two deflecting cavity to chirp the electron pulse and then generate short pulse x-ray. To minimize the influence to other users on the storage ring, the phase synchronization of the two deflecting cavity are required to be better then 77 femto-second. A LLRF4 board based system is designed to demonstrate the capability of meeting this requirement. This paper discuss the hardware and firmware design of the demo experiment including the cavity emulator, frequency reference generation and LLRF control algorithm.