ICALEPCS2017 - List of Authors (Vasquez, J.A.)

Paper	Title	Page
TUPHA014	Booster RF Upgrade for SPEAR3	401
	S. Condamoor, S. Allison, J.J. Sebek, J.A. Vásquez, J.V. Wachter SLAC, Menlo Park, California, USA
	Funding: Work is supported by the U.S. Department of Energy, Office of Science under Contract DE-AC02-76SF00515 SLAC's SPEAR3 Booster RF system was recently upgraded where the existing klystron providing RF power to a 5-cell cavity was replaced with a Solid State Amplifier (SSA). The Low Level RF Controls (LLRF) to drive the SSA was provided by a high performance FPGA based system built on SLAC ATCA modules. RF Cavity Tuner Controls were replaced with EtherCAT-based stepper motor controller. New hardware was designed and built for PLC-based Machine Protection System (MPS). Fast digitizers to sample and acquire LLRF signals were implemented in a LinuxRT Server. All of these required new Controls Software implementation. This poster illustrates the Controls associated with each of the above hardware.
	Poster TUPHA014 [0.895 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA014
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THMPL08	The SLAC Common-Platform Firmware for High-Performance Systems	1286
	T. Straumann, R. Claus, J.M. D'Ewart, J.C. Frisch, G. Haller, R.T. Herbst, B. Hong, U. Legat, L. Ma, J.J. Olsen, B.A. Reese, R. Ruckman, L. Sapozhnikov, S.R. Smith, D. Van Winkle, J.A. Vásquez, M. Weaver, E. Williams, C. Xu, A. Young SLAC, Menlo Park, California, USA
	Funding: Work supported by the US Department of Energy, Office of Science under contract DE-AC02-76SF00515 LCLS-II's high beam rate of almost 1MHz and the requirement that several "high-performance" systems (such as MPS, BPM, LLRF, timing etc.) shall resolve individual bunches precludes the use of a traditional software based control system but requires many core services to be implemented in FPGA logic. SLAC has created a comprehensive open-source firmware framework which implements many commonly used blocks (e.g., timing, globally-synchronized fast data buffers, MPS, diagnostic data capture), libraries (Ethernet protocol stack, AXI interconnect, FIFOs, memory etc.) and interfaces (e.g., for timing, diagnostic data etc.) thus providing a versatile platform on top of which powerful high-performance systems can be built and rapidly integrated.
	Slides THMPL08 [0.579 MB]
	Poster THMPL08 [0.630 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL08
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA138	YCPSWASYN: EPICS Driver for FPGA Register Access and Asynchronous Messaging	1707
	J.A. Vásquez, J.M. D'Ewart, K.H. Kim, T. Straumann, E. Williams SLAC, Menlo Park, California, USA
	The Linac Coherent Light Source II (LCLS-II) is a major upgrade of the LCLS facility at SLAC, scheduled to start operations in 2020. The High Performance Systems (HPS) defines a set of LCLS-II controls sub-systems which are directly impacted by its 1 MHz operation. It is formed around a few key concepts: ATCA based packaging, digital and analog application boards, and 10G Ethernet based interconnections for controls. The Common Platform provides the common parts of the HPS in term of hardware, firmware, and software. The Common Platform Software (CPSW) provides a standardized interface to the common platform's FPGA for all high-level software. YAML is used to define the hardware topology and all necessary parameters. YCPSWASYN is an asynPortDriver based EPICS module for FPGA register access and asynchronous messaging using CPSW. YCPSWSYN has two operation modes: an automatic mode where PVs are automatically created for all registers and the record's fields are populated with information found in YAML; and a manual mode where the engineer can choose which register to expose via PVs and freely choose the record's filed information.
	Poster THPHA138 [1.189 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA138
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Booster RF Upgrade for SPEAR3

401

S. Condamoor, S. Allison, J.J. Sebek, J.A. Vásquez, J.V. Wachter
SLAC, Menlo Park, California, USA

Funding: Work is supported by the U.S. Department of Energy, Office of Science under Contract DE-AC02-76SF00515
SLAC's SPEAR3 Booster RF system was recently upgraded where the existing klystron providing RF power to a 5-cell cavity was replaced with a Solid State Amplifier (SSA). The Low Level RF Controls (LLRF) to drive the SSA was provided by a high performance FPGA based system built on SLAC ATCA modules. RF Cavity Tuner Controls were replaced with EtherCAT-based stepper motor controller. New hardware was designed and built for PLC-based Machine Protection System (MPS). Fast digitizers to sample and acquire LLRF signals were implemented in a LinuxRT Server. All of these required new Controls Software implementation. This poster illustrates the Controls associated with each of the above hardware.

Poster TUPHA014 [0.895 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA014

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THMPL08

The SLAC Common-Platform Firmware for High-Performance Systems

1286

T. Straumann, R. Claus, J.M. D'Ewart, J.C. Frisch, G. Haller, R.T. Herbst, B. Hong, U. Legat, L. Ma, J.J. Olsen, B.A. Reese, R. Ruckman, L. Sapozhnikov, S.R. Smith, D. Van Winkle, J.A. Vásquez, M. Weaver, E. Williams, C. Xu, A. Young
SLAC, Menlo Park, California, USA

Funding: Work supported by the US Department of Energy, Office of Science under contract DE-AC02-76SF00515
LCLS-II's high beam rate of almost 1MHz and the requirement that several "high-performance" systems (such as MPS, BPM, LLRF, timing etc.) shall resolve individual bunches precludes the use of a traditional software based control system but requires many core services to be implemented in FPGA logic. SLAC has created a comprehensive open-source firmware framework which implements many commonly used blocks (e.g., timing, globally-synchronized fast data buffers, MPS, diagnostic data capture), libraries (Ethernet protocol stack, AXI interconnect, FIFOs, memory etc.) and interfaces (e.g., for timing, diagnostic data etc.) thus providing a versatile platform on top of which powerful high-performance systems can be built and rapidly integrated.

Slides THMPL08 [0.579 MB]

Poster THMPL08 [0.630 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL08

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA138

YCPSWASYN: EPICS Driver for FPGA Register Access and Asynchronous Messaging

1707

J.A. Vásquez, J.M. D'Ewart, K.H. Kim, T. Straumann, E. Williams
SLAC, Menlo Park, California, USA

The Linac Coherent Light Source II (LCLS-II) is a major upgrade of the LCLS facility at SLAC, scheduled to start operations in 2020. The High Performance Systems (HPS) defines a set of LCLS-II controls sub-systems which are directly impacted by its 1 MHz operation. It is formed around a few key concepts: ATCA based packaging, digital and analog application boards, and 10G Ethernet based interconnections for controls. The Common Platform provides the common parts of the HPS in term of hardware, firmware, and software. The Common Platform Software (CPSW) provides a standardized interface to the common platform's FPGA for all high-level software. YAML is used to define the hardware topology and all necessary parameters. YCPSWASYN is an asynPortDriver based EPICS module for FPGA register access and asynchronous messaging using CPSW. YCPSWSYN has two operation modes: an automatic mode where PVs are automatically created for all registers and the record's fields are populated with information found in YAML; and a manual mode where the engineer can choose which register to expose via PVs and freely choose the record's filed information.

Poster THPHA138 [1.189 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA138

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)