ICALEPCS2017 - List of Authors (Rutkowski, I.)

Paper	Title	Page
THPHA081	LO Board for 704.42 MHz Cavity Simulator for ESS	1573
	I. Rutkowski, K. Czuba, M.G. Grzegrzolka Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
	Funding: Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2016/03 This paper describes the requirements, architecture, and measurements results of the local oscillator (LO) board prototype. The design will provide low phase noise clock and heterodyne signals for the 704.42 MHz Cavity Simulator for the European Spallation Source. A field detection has critical influence on the simulation's performance and its quality depends on the quality of the two aforementioned signals. The clock frequency is a subharmonic of the reference frequency and choice of the frequency divider generating the clock signals is discussed. The performance of selected dividers was compared. The LO frequency must be synthesized and frequency synthesis schemes are investigated. Critical components used in the direct analog scheme are identified and their selection criteria were given.
	Poster THPHA081 [1.406 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA081
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA123	Concept of Cavity Simulator for European Spallation Source	1666
	M.G. Grzegrzolka, K. Czuba, I. Rutkowski Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
	At the European Spallation Source it is foreseen to use around 120 superconducting cavities operating at 704.42 MHz. Each cavity will require an individual LLRF control system, that needs to be tested before the installation inside the accelerator. Testing of all systems using the real superconducting cavities would be very expensive and in case of a failure can lead to serious damages. To lower the testing cost and avoid potential risks it is planned to design and build a device that simulates the behavior of a superconducting cavity. The cavity simulator will utilize fast data converters equipped with an RF front-end and a digital signal processing unit based on a high performance FPGA. In this paper conceptual design of hardware and firmware will be presented.
	Poster THPHA123 [1.500 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA123
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

LO Board for 704.42 MHz Cavity Simulator for ESS

1573

I. Rutkowski, K. Czuba, M.G. Grzegrzolka
Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland

Funding: Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2016/03
This paper describes the requirements, architecture, and measurements results of the local oscillator (LO) board prototype. The design will provide low phase noise clock and heterodyne signals for the 704.42 MHz Cavity Simulator for the European Spallation Source. A field detection has critical influence on the simulation's performance and its quality depends on the quality of the two aforementioned signals. The clock frequency is a subharmonic of the reference frequency and choice of the frequency divider generating the clock signals is discussed. The performance of selected dividers was compared. The LO frequency must be synthesized and frequency synthesis schemes are investigated. Critical components used in the direct analog scheme are identified and their selection criteria were given.

Poster THPHA081 [1.406 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA081

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA123

Concept of Cavity Simulator for European Spallation Source

1666

M.G. Grzegrzolka, K. Czuba, I. Rutkowski
Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland

At the European Spallation Source it is foreseen to use around 120 superconducting cavities operating at 704.42 MHz. Each cavity will require an individual LLRF control system, that needs to be tested before the installation inside the accelerator. Testing of all systems using the real superconducting cavities would be very expensive and in case of a failure can lead to serious damages. To lower the testing cost and avoid potential risks it is planned to design and build a device that simulates the behavior of a superconducting cavity. The cavity simulator will utilize fast data converters equipped with an RF front-end and a digital signal processing unit based on a high performance FPGA. In this paper conceptual design of hardware and firmware will be presented.

Poster THPHA123 [1.500 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA123

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)