ICALEPCS2019 - List of Authors (Carlier, E.)

Paper	Title	Page
MOPHA088	Consolidation of Re-Triggering System of LHC Beam Dumping System at CERN	412
	N. Magnin, W. Bartmann, C. Bracco, E. Carlier, G. Gräwer, T.D. Mottram, E. Renner, Rodziewicz, J.P. Rodziewicz, V. Senaj, C. Wiesner CERN, Geneva, Switzerland
	The Trigger Synchronization and Distribution System (TSDS) is a core part of the LHC Beam Dump System (LBDS). It comprises redundant Re-Trigger Lines (RTLs) that allow fast re-triggering of all high-voltage pulsed generators in case one self-triggers, resulting in a so-called asynchronous dump. For reliability reasons, the TSDS relies on many RTL redundant trigger sources that do not participate directly to the execution of a normal dump. After every dump, signals propagating on the RTLs are analyzed by Post Operation Check (POC) systems, to validate the correct performance and synchronization of all redundant triggers. The LBDS operated reliably since the start-up of LHC in 2008, but during the Run 2 of the LHC, new failure modes were identified that could incur damage for the beam dump block. In order to correct these failure modes, an upgrade of the TSDS is realized during the LS2. This paper reviews the experience gained with the LBDS during Run 2 of the LHC operation and describes the new architecture of the TSDS being implemented. Measurements and simulations of signals propagating on the RTL are presented, and the analysis performed by the POC systems are explained.
	Poster MOPHA088 [2.435 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA088
About •	paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA113	Linux-based PXIe System for the Real-Time Control of New Painting Bumper at CERN	483
	M.P. Pimentel, E. Carlier, C. Chanavat, T. Gharsa, G. Gräwer, N. Magnin, N. Voumard CERN, Geneva, Switzerland
	In the framework of the LHC Injectors Upgrade Project, the new connection from Linac4, injecting a 160 MeV H⁻ beam into the Proton Synchrotron Booster (PSB) requires a set of four slow kicker magnets (KSW) per PSB ring to move the beam on a stripping foil, remove electrons and perform phase space painting. A new multiple-linear waveform generator based on a Marx topology powers each KSW, allowing adjustment of the current discharge shape with high flexibility for the different beam users. To control these complex power generators, National Instruments (NI) PXIe crates fitted with a set of modules (A/D, D/A, FPGA, PROFINET) are used. Initially, control software developed with LabVIEW has validated the test bench hardware. A full software re-engineering, accessing the hardware using Linux drivers, C APIs and the C++ framework FESA3 under Linux CentOS7 was achieved for operational deployment. This paper describes the hardware used, and the integration of NI PXIe systems into CERN controls environment, as well as the software architecture to access the hardware and provide PSB operators and kicker experts with the required control and supervision.
	Poster MOPHA113 [1.081 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA113
About •	paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA153	SoC Technology for Embedded Control and Interlocking Within Fast Pulsed Systems at CERN	592
	P. Van Trappen, E. Carlier, M. Gauthier, N. Magnin, E.J. Oltedal, J. Schipper CERN, Geneva, Switzerland
	The control of pulsed systems at CERN requires often the use of fast digital electronics to perform tight timing control and fast protection of high-voltage pulsed generators. For the implementation of such functionalities, a FPGA is the perfect candidate for the digital logic, however with limited integration potential within the control system. The market push for integrated devices, so called System on a Chip (SoC) - a tightly coupled ARM processing system and specific programmable logic in a single device, has allowed a better integration of the various components required for the control of pulsed systems. This technology is used for the implementation of fast switch interlocking logic, integrated within the CERN control framework by using embedded Linux running a Snap7 server. It is also used for the implementation of a lower-tier communication bridge between a front-end computer and a high fan-out multiplexing programmable logic for timing and analogue low-level control. This paper presents these two projects where the SoC technology has been deployed and discusses possible further applications within distributed real-time control architecture for distributed pulsed systems.
	Poster MOPHA153 [0.828 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA153
About •	paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Consolidation of Re-Triggering System of LHC Beam Dumping System at CERN

412

N. Magnin, W. Bartmann, C. Bracco, E. Carlier, G. Gräwer, T.D. Mottram, E. Renner, Rodziewicz, J.P. Rodziewicz, V. Senaj, C. Wiesner
CERN, Geneva, Switzerland

The Trigger Synchronization and Distribution System (TSDS) is a core part of the LHC Beam Dump System (LBDS). It comprises redundant Re-Trigger Lines (RTLs) that allow fast re-triggering of all high-voltage pulsed generators in case one self-triggers, resulting in a so-called asynchronous dump. For reliability reasons, the TSDS relies on many RTL redundant trigger sources that do not participate directly to the execution of a normal dump. After every dump, signals propagating on the RTLs are analyzed by Post Operation Check (POC) systems, to validate the correct performance and synchronization of all redundant triggers. The LBDS operated reliably since the start-up of LHC in 2008, but during the Run 2 of the LHC, new failure modes were identified that could incur damage for the beam dump block. In order to correct these failure modes, an upgrade of the TSDS is realized during the LS2. This paper reviews the experience gained with the LBDS during Run 2 of the LHC operation and describes the new architecture of the TSDS being implemented. Measurements and simulations of signals propagating on the RTL are presented, and the analysis performed by the POC systems are explained.

Poster MOPHA088 [2.435 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA088

About •

paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA113

Linux-based PXIe System for the Real-Time Control of New Painting Bumper at CERN

483

M.P. Pimentel, E. Carlier, C. Chanavat, T. Gharsa, G. Gräwer, N. Magnin, N. Voumard
CERN, Geneva, Switzerland

In the framework of the LHC Injectors Upgrade Project, the new connection from Linac4, injecting a 160 MeV H⁻ beam into the Proton Synchrotron Booster (PSB) requires a set of four slow kicker magnets (KSW) per PSB ring to move the beam on a stripping foil, remove electrons and perform phase space painting. A new multiple-linear waveform generator based on a Marx topology powers each KSW, allowing adjustment of the current discharge shape with high flexibility for the different beam users. To control these complex power generators, National Instruments (NI) PXIe crates fitted with a set of modules (A/D, D/A, FPGA, PROFINET) are used. Initially, control software developed with LabVIEW has validated the test bench hardware. A full software re-engineering, accessing the hardware using Linux drivers, C APIs and the C++ framework FESA3 under Linux CentOS7 was achieved for operational deployment. This paper describes the hardware used, and the integration of NI PXIe systems into CERN controls environment, as well as the software architecture to access the hardware and provide PSB operators and kicker experts with the required control and supervision.

Poster MOPHA113 [1.081 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA113

About •

paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA153

SoC Technology for Embedded Control and Interlocking Within Fast Pulsed Systems at CERN

592

P. Van Trappen, E. Carlier, M. Gauthier, N. Magnin, E.J. Oltedal, J. Schipper
CERN, Geneva, Switzerland

The control of pulsed systems at CERN requires often the use of fast digital electronics to perform tight timing control and fast protection of high-voltage pulsed generators. For the implementation of such functionalities, a FPGA is the perfect candidate for the digital logic, however with limited integration potential within the control system. The market push for integrated devices, so called System on a Chip (SoC) - a tightly coupled ARM processing system and specific programmable logic in a single device, has allowed a better integration of the various components required for the control of pulsed systems. This technology is used for the implementation of fast switch interlocking logic, integrated within the CERN control framework by using embedded Linux running a Snap7 server. It is also used for the implementation of a lower-tier communication bridge between a front-end computer and a high fan-out multiplexing programmable logic for timing and analogue low-level control. This paper presents these two projects where the SoC technology has been deployed and discusses possible further applications within distributed real-time control architecture for distributed pulsed systems.

Poster MOPHA153 [0.828 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA153

About •

paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)