PCaPAC2012 - List of Authors (Chatterjee, A.)

Paper

Title

Page

Development of Data Acquisition Software for VME Based System

35

A. Kumar, A. Chatterjee, K. Mahata, K. Ramachandran
BARC, Mumbai, India

A Data Acquisition system for VME has been developed for use in accelerator based experiments. It is in use at BARC-TIFR laboratory. The development was motivated by the growing demand for higher throughput in view of the increasing size of experiments. The VME based data acquisition system provides a powerful alternative to CAMAC standards on account of higher readout speeds (100 ns/word) resulting in reduced dead time. Further, high density VME modules are capable of providing up to 640 channels in a single VME crate with 21 slots. The software system LAMPS[1], earlier developed for CAMAC based system and used extensively in our laboratory and elsewhere has been modified for the present VME based system. The system makes use of the VME library to implement Chain Block Transfer Readout (CBLT) and gives the option of both Polling and Interrupt mode to acquire data. Practical throughput of ~250 ns/word in zero-suppressed mode have been achieved. The developed software currently supports CAEN[2] V785 ADC, V775 TDC and V862 QDC and V830 Scalar Modules. The design, development and architecture of this DAQ system will be discussed.
[1] http://www.tifr.res.in/~pell/lamps.html
[2] http://caen.it/

FRCC02

A FPGA Based High Speed Data Acquisition Card

271

J.A. Gore, P. V. Bhagwat, A. Chatterjee, S. Kailas, S. Kulkarni, K. Mahata, S.K. Pandit, V.V. Parkar, A. Shrivastava
BARC, Mumbai, India

Funding: Bhabha Atomic Research Centre, Nuclear Physics Division
A FPGA based, high speed,two channel,analog input card with a maximum input sampling rate of 1 Giga samples per second (Gsps)per channel has been designed and tested. The card has got an on-board cPCI interface but has been designed in a way that it can also work as a stand-alone system. The card can function as a platform for developing and evaluating different FPGA based hardware designs. Recently, the card has been used to develop a direct sampling Low Level RF (LLRF) controller for controlling the electromagnetic fields of a prototype heavy ion RFQ. It has also been tested for acquisition of data in nuclear physics experiments. Pulses from surface barrier and silicon strip detectors were acquired at an input sampling rate of 1 Gs/s employing ²⁴¹Am and Am-Pu sources. The design developed for this makes use of pre-triggering. This paper discusses the functionality, salient design issues and features of the card. Finally the hardware designs of above mentioned applications related to different areas of LLRF control and nuclear pulse acquisition are explained and the results obtained are presented.

Slides FRCC02 [1.431 MB]

Paper	Title	Page
WEPD16	Development of Data Acquisition Software for VME Based System	35
	A. Kumar, A. Chatterjee, K. Mahata, K. Ramachandran BARC, Mumbai, India
	A Data Acquisition system for VME has been developed for use in accelerator based experiments. It is in use at BARC-TIFR laboratory. The development was motivated by the growing demand for higher throughput in view of the increasing size of experiments. The VME based data acquisition system provides a powerful alternative to CAMAC standards on account of higher readout speeds (100 ns/word) resulting in reduced dead time. Further, high density VME modules are capable of providing up to 640 channels in a single VME crate with 21 slots. The software system LAMPS[1], earlier developed for CAMAC based system and used extensively in our laboratory and elsewhere has been modified for the present VME based system. The system makes use of the VME library to implement Chain Block Transfer Readout (CBLT) and gives the option of both Polling and Interrupt mode to acquire data. Practical throughput of ~250 ns/word in zero-suppressed mode have been achieved. The developed software currently supports CAEN[2] V785 ADC, V775 TDC and V862 QDC and V830 Scalar Modules. The design, development and architecture of this DAQ system will be discussed. [1] http://www.tifr.res.in/~pell/lamps.html [2] http://caen.it/

FRCC02	A FPGA Based High Speed Data Acquisition Card	271
	J.A. Gore, P. V. Bhagwat, A. Chatterjee, S. Kailas, S. Kulkarni, K. Mahata, S.K. Pandit, V.V. Parkar, A. Shrivastava BARC, Mumbai, India
	Funding: Bhabha Atomic Research Centre, Nuclear Physics Division A FPGA based, high speed,two channel,analog input card with a maximum input sampling rate of 1 Giga samples per second (Gsps)per channel has been designed and tested. The card has got an on-board cPCI interface but has been designed in a way that it can also work as a stand-alone system. The card can function as a platform for developing and evaluating different FPGA based hardware designs. Recently, the card has been used to develop a direct sampling Low Level RF (LLRF) controller for controlling the electromagnetic fields of a prototype heavy ion RFQ. It has also been tested for acquisition of data in nuclear physics experiments. Pulses from surface barrier and silicon strip detectors were acquired at an input sampling rate of 1 Gs/s employing ²⁴¹Am and Am-Pu sources. The design developed for this makes use of pre-triggering. This paper discusses the functionality, salient design issues and features of the card. Finally the hardware designs of above mentioned applications related to different areas of LLRF control and nuclear pulse acquisition are explained and the results obtained are presented.
	Slides FRCC02 [1.431 MB]