• B.R. Park, J. Choi, M.-H. Chun, Y.J. Han, M.H. Jeong, S.-C. Kim, J.S. Yang, I.H. Yu
  PAL, Pohang, Kyungbuk

Sequence control system of 1-MW CW klystron for the PEFP (Proton Engineering Frontier Project) has been developed in order to drive the 1-MW klystron amplifier. The system is able to control several power supplies and many environment conditions. The hardware of sequence control and the interlock system are based on the Allen-Bradley's SLC500 Program Logic Controller (PLC). Also the system can be controlled by a touch screen at local mode or Ethernet network with high level HMI at remote mode.

• I.H. Yu, Y.J. Han, H.-S. Kang, D.T. Kim, S.-C. Kim, I.-S. Park, J.C. Yoon
  PAL, Pohang, Kyungbuk
• Y.-S. Cho, H.-J. Kwon, K.T. Seol
  KAERI, Daejon

The 100 MeV Proton linear accelerator (Linac) for the PEFP (Proton Engineering Frontier Project) will include 1 RFQ and 1 DTL1 at 350 MHz as well as 7 DTL2 cavities at 700 MHz. The low level RF system with the digital feedback RF control provides the field control to accelerate a 20mA proton beam from 50 keV to 20 MeV with a RFQ and a DTL1 at 350M Hz. The FPGA-based digital feedback RF control system has been built and is used to control cavity field amplitude within ± 1% and relative phase within ± 1°. The fast digital processing is networked to the EPICS-based control system with an embedded processor (Blackfin). In this paper, the detailed description of the digital feedback RF control system will be described with the performance test results.

• I.H. Yu, D.T. Kim, S.-C. Kim, I.-S. Park, S.J. Park
  PAL, Pohang, Kyungbuk
• Y.-S. Cho
  KAERI, Daejon

The PEFP (Proton Engineering Frontier Project) at the KAERI (Korea Atomic Energy Research Institute) is building a high-power proton linear accelerator aiming to generate 100-MeV proton beams with 20-mA peak current (pulse width and max. repetition rate of 1 ms and 120 Hz respectively). We are developing a prototype digital BPPM (Beam Position and Phase Monitor) for the PEFP linac utilizing the digital technology with field programmable gate array (FPGA). The RF input signals are down converted to 10 MHz and sampled at 40 MHz with 14-bit ADC to produce I and Q data streams. The system is designed to provide a position and phase resolution of 0.1% and 0.1? RMS respectively. The fast digital processing is networked to the EPICS-based control system with an embedded processor (Blackfin). In this paper, the detailed description of the prototype digital beam position and phase monitor will be described with the performance test results.