Author: Mounts, C.I.
Paper Title Page
THPAB271 JLAB LLRF 3.0 Development and Tests 4340
 
  • T.E. Plawski, R. Bachimanchi, S. Higgins, C. Hovater, J. Latshaw, C.I. Mounts, D.J. Seidman, J. Yan
    JLab, Newport News, Virginia, USA
  
  The Jef­fer­son Lab LLRF 3.0 sys­tem is being de­vel­oped to re­place legacy LLRF sys­tems in the CEBAF ac­cel­er­a­tor. The new de­sign builds upon 25 years of de­sign and op­er­a­tional RF con­trol ex­pe­ri­ence, and our re­cent col­lab­o­ra­tion in the de­sign of the LCLSII LLRF sys­tem. The new cav­ity con­trol al­go­rithm is a fully func­tional phase and am­pli­tude locked Self Ex­cit­ing Loop (SEL). This paper dis­cusses the progress of the LLRF 3.0 hard­ware de­sign, FPGA firmware de­vel­op­ment, User Data­gram Pro­to­col (UDP) op­er­a­tion, and re­cent LLRF 3.0 sys­tem tests on the CEBAF Booster cry­omod­ule in the Up­grade In­jec­tor Test Fa­cil­ity (UITF).  
poster icon Poster THPAB271 [1.940 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2021-THPAB271  
About • paper received ※ 14 May 2021       paper accepted ※ 06 July 2021       issue date ※ 20 August 2021  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)