ICALEPCS2017 - List of Authors (Weaver, M.)

Paper	Title	Page
TUMPL04	LCLS-II Timing Pattern Generator Configuration GUIs	307
	C. Bianchini, J. Browne, K.H. Kim, P. Krejcik, M. Weaver, S. Zelazny SLAC, Menlo Park, California, USA
	The LINAC Coherent Light Source II (LCLS-II) is an upgrade of the SLAC National Accelerator Laboratory LCLS facility to a superconducting LINAC with multiple destinations at different power levels. The challenge in delivering timing to a superconducting LINAC is dictated by the stability requirements for the beam power and the 1MHz rate. A timing generator will produce patterns instead of events because of the large number of event codes required. The poster explains how the stability requirements are addressed by the design of two Graphical User Interfaces (GUI). The Allow Table GUI filters the timing pattern requests respecting the Machine Protection System (MPS) defined Power Class and the electron beam dump capacities. The Timing Pattern Generator (TPG) programs Sequence Engines to deliver the beam rate configuration requested by the user. The low level program, The TPG generates the patterns, which contains the timing information propagated to the Timing Pattern Receiver (TPR). Both are implemented with an FPGA solution and configured by EPICS. The poster shows an overall design of the high-level software solutions that meet the physics requirements for LCLS-II timing.
	Slides TUMPL04 [1.030 MB]
	Poster TUMPL04 [0.883 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL04
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THMPL08	The SLAC Common-Platform Firmware for High-Performance Systems	1286
	T. Straumann, R. Claus, J.M. D'Ewart, J.C. Frisch, G. Haller, R.T. Herbst, B. Hong, U. Legat, L. Ma, J.J. Olsen, B.A. Reese, R. Ruckman, L. Sapozhnikov, S.R. Smith, D. Van Winkle, J.A. Vásquez, M. Weaver, E. Williams, C. Xu, A. Young SLAC, Menlo Park, California, USA
	Funding: Work supported by the US Department of Energy, Office of Science under contract DE-AC02-76SF00515 LCLS-II's high beam rate of almost 1MHz and the requirement that several "high-performance" systems (such as MPS, BPM, LLRF, timing etc.) shall resolve individual bunches precludes the use of a traditional software based control system but requires many core services to be implemented in FPGA logic. SLAC has created a comprehensive open-source firmware framework which implements many commonly used blocks (e.g., timing, globally-synchronized fast data buffers, MPS, diagnostic data capture), libraries (Ethernet protocol stack, AXI interconnect, FIFOs, memory etc.) and interfaces (e.g., for timing, diagnostic data etc.) thus providing a versatile platform on top of which powerful high-performance systems can be built and rapidly integrated.
	Slides THMPL08 [0.579 MB]
	Poster THMPL08 [0.630 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL08
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

LCLS-II Timing Pattern Generator Configuration GUIs

307

C. Bianchini, J. Browne, K.H. Kim, P. Krejcik, M. Weaver, S. Zelazny
SLAC, Menlo Park, California, USA

The LINAC Coherent Light Source II (LCLS-II) is an upgrade of the SLAC National Accelerator Laboratory LCLS facility to a superconducting LINAC with multiple destinations at different power levels. The challenge in delivering timing to a superconducting LINAC is dictated by the stability requirements for the beam power and the 1MHz rate. A timing generator will produce patterns instead of events because of the large number of event codes required. The poster explains how the stability requirements are addressed by the design of two Graphical User Interfaces (GUI). The Allow Table GUI filters the timing pattern requests respecting the Machine Protection System (MPS) defined Power Class and the electron beam dump capacities. The Timing Pattern Generator (TPG) programs Sequence Engines to deliver the beam rate configuration requested by the user. The low level program, The TPG generates the patterns, which contains the timing information propagated to the Timing Pattern Receiver (TPR). Both are implemented with an FPGA solution and configured by EPICS. The poster shows an overall design of the high-level software solutions that meet the physics requirements for LCLS-II timing.

Slides TUMPL04 [1.030 MB]

Poster TUMPL04 [0.883 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL04

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THMPL08

The SLAC Common-Platform Firmware for High-Performance Systems

1286

T. Straumann, R. Claus, J.M. D'Ewart, J.C. Frisch, G. Haller, R.T. Herbst, B. Hong, U. Legat, L. Ma, J.J. Olsen, B.A. Reese, R. Ruckman, L. Sapozhnikov, S.R. Smith, D. Van Winkle, J.A. Vásquez, M. Weaver, E. Williams, C. Xu, A. Young
SLAC, Menlo Park, California, USA

Funding: Work supported by the US Department of Energy, Office of Science under contract DE-AC02-76SF00515
LCLS-II's high beam rate of almost 1MHz and the requirement that several "high-performance" systems (such as MPS, BPM, LLRF, timing etc.) shall resolve individual bunches precludes the use of a traditional software based control system but requires many core services to be implemented in FPGA logic. SLAC has created a comprehensive open-source firmware framework which implements many commonly used blocks (e.g., timing, globally-synchronized fast data buffers, MPS, diagnostic data capture), libraries (Ethernet protocol stack, AXI interconnect, FIFOs, memory etc.) and interfaces (e.g., for timing, diagnostic data etc.) thus providing a versatile platform on top of which powerful high-performance systems can be built and rapidly integrated.

Slides THMPL08 [0.579 MB]

Poster THMPL08 [0.630 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL08

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)