Author: Ibarra, A.
Paper Title Page
MOPMS009 IFMIF LLRF Control System Architecture Based on Epics 339
 
  • J.C. Calvo, A. Ibarra, A. Salom
    CIEMAT, Madrid, Spain
  • M.A. Patricio
    UCM, Colmenarejo, Spain
  • M.L. Rivers
    ANL, Argonne, USA
  
  The IFMIF-EVE­DA (In­ter­na­tion­al Fu­sion Ma­te­ri­als Ir­ra­di­a­tion Fa­cil­i­ty - En­gi­neer­ing Val­i­da­tion and En­gi­neer­ing De­sign Ac­tiv­i­ty) lin­ear ac­cel­er­a­tor will be a 9 MeV, 125mA CW (Con­tin­u­ous Wave) deuteron ac­cel­er­a­tor pro­to­type to val­i­date the tech­ni­cal op­tions of the ac­cel­er­a­tor de­sign for IFMIF. The RF (Radio Fre­quen­cy) power sys­tem of IFMIF-EVE­DA con­sists of 18 RF chains work­ing at 175MHz with three am­pli­fi­ca­tion stages each; each one of the re­quired chains for the ac­cel­er­a­tor pro­to­type is based on sev­er­al 175MHz am­pli­fi­ca­tion stages. The LLRF sys­tem pro­vides the RF Drive input of the RF plants. It con­trols the am­pli­tude and phase of this sig­nal to be syn­chro­nized with the beam and it also con­trols the res­o­nance fre­quen­cy of the cav­i­ties. The sys­tem is based on a com­mer­cial cPCI FPGA Board pro­vid­ed by Lyrtech and con­trolled by a Win­dows Host PC. For this pur­pose, it is manda­to­ry to com­mu­ni­cate the cPCI FPGA Board with an EPICS Chan­nel Ac­cess, build­ing an IOC (Input Out­put Con­troller) be­tween Lyrtech board and EPICS. A new soft­ware ar­chi­tec­ture to de­sign a de­vice sup­port, using Asyn­Port­Driv­er class and CSS as a GUI (Graph­i­cal User In­ter­face), is pre­sent­ed.  
poster icon Poster MOPMS009 [2.763 MB]