cathode

Paper	Title	Other Keywords	Page
TPPB38	Status of the ERLP Control System	controls, laser, linac, vacuum	244
	G. Cox, A. Oates STFC/DL, Daresbury, Warrington, Cheshire S. V. Davis, A. J. Duggan, A. Quigley, R. V. Rotheroe, B. G. Martlew STFC/DL/SRD, Daresbury, Warrington, Cheshire
	The Energy Recovery Linac Prototype (ERLP) is a 35 Mev superconducting linac currently being commissioned at Daresbury Laboratory. Its purpose is to demonstrate the technology necessary to design and build a 600 Mev energy recovery linac (4GLS), which, together with a suite of XUV, VUV, and IR FELs, can be used to undertake pump-probe experiments to investigate dynamic systems. The ERLP control system is based on EPICS, VME64x hardware, and the vxWorks operating system. Status control and interlock protection are handled by a Daresbury-designed CANbus system that has been tightly integrated into EPICS. Construction and commissioning of ERLP have taken place in parallel, and this introduced a number of problems in the planning and implementation of the control system. This paper describes the ERLP control system and disusses the successes and difficulties encountered during the early phases of commissioning. Plans are already in place to extend the control system to cover EMMA, a novel, non-scaling, fixed-field alternating gradient (FFAG) accelerator that will be added to ERLP in 2008/9.
FOAB02	Digital Phase Control System for SSRF Linac	controls, klystron, linac, background	717
	D. K. Liu, L. Y. Yu, C. X. Yin SINAP, Shanghai
	SSRF 150MeV linac includes two klystrons and two solid power amplifers, which drive two klystrons, respectively. The accelerating section is constant gradient accelerating structure, and its working frequency is 2998MHz, six times the storage ring RF frequency. In order to reach the requirement for the RF phase stability (±1 degree), the full digital phase control system, which includes RF front-end, AD, DA, and FPGA, is designed. FPGA, the key for phase control system, contains digital I/Q demoulator (phase detector), digital I/Q modulator (phase shifter), and control algorithms. Klystron forward signal is down converted to IF (12.5MHz), which is detected by ADC with 50MHz clock. Digital I/Q is generated by ADC sampling data and then sent to control algorithms in FPGA. After processed by control algorithms, digital I/Q is converted to IF by DAC (50MHz). IF signal from DAC output is up converted to RF and sent to solid RF power amplifer. With the aid of FPGA, the whole period of closed-loop is about 80ns, and delay of closed-loop is less than 600ns. The test results of digital phase control system are presented in this paper.
	Slides