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| TPPB20 |
SSRF Beam Instrumentations System
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205 |
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- J. Chen, Y. Z. Chen, Z. C. Chen, D. K. Liu, K. R. Ye, C. X. Yin, J. Yu, L. Y. Yu, R. Yuan, G. B. Zhao, W. M. Zhou, Y. Zou, Y. B. Leng
SINAP, Shanghai
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SSRF is equipped with various beam instrumentations, in which the Linac part has been working well since the start of the commissioning this year, and the booster and storage ring parts are still under implementation and commissioning. The commercial products were adopted to build this system as much as possible. The all-in-one electron beam position monitor processor, Libera, was used for whole facility to provide single-pass, first-turn, turn-by-turn, COD, and fast application beam position data. The Bergoz NPCT175 parametric current transformers were used for DC current measurement in the booster and storage ring. The various optical beam diagnostic systems, such as synchrotron radiation interferometers for precise beam-size measurement, the fast gated camera, and the bunch length monitor will be equipped in the dedicated diagnostics beam line. Data acquisition for beam instrumentation system should be a part of control system, developed on an EPICS platform. There are three kinds of Input Output Controllers (IOCs) used in diagnostics: VxWorks-based VME IOCs, Linux-based Libera IOCs, and Windows-based PC IOCs.
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| FOAB02 |
Digital Phase Control System for SSRF Linac
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717 |
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- D. K. Liu, L. Y. Yu, C. X. Yin
SINAP, Shanghai
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SSRF 150MeV linac includes two klystrons and two solid power amplifers, which drive two klystrons, respectively. The accelerating section is constant gradient accelerating structure, and its working frequency is 2998MHz, six times the storage ring RF frequency. In order to reach the requirement for the RF phase stability (±1 degree), the full digital phase control system, which includes RF front-end, AD, DA, and FPGA, is designed. FPGA, the key for phase control system, contains digital I/Q demoulator (phase detector), digital I/Q modulator (phase shifter), and control algorithms. Klystron forward signal is down converted to IF (12.5MHz), which is detected by ADC with 50MHz clock. Digital I/Q is generated by ADC sampling data and then sent to control algorithms in FPGA. After processed by control algorithms, digital I/Q is converted to IF by DAC (50MHz). IF signal from DAC output is up converted to RF and sent to solid RF power amplifer. With the aid of FPGA, the whole period of closed-loop is about 80ns, and delay of closed-loop is less than 600ns. The test results of digital phase control system are presented in this paper.
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Slides
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