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Someya, H.

Paper Title Page
WPPB14 Development of a Signal Processing Board for Spill Digital Servo System for Proton Synchrotron 430
  • T. Adachi, R. Muto, H. Sato, H. Someya, M. Tomizawa, H. Nakagawa
    KEK, Ibaraki
  • T. I. Ichikawa, K. Mochiki
    Musasi Institute of Technology, Instrumentation and Control Laboratory, Tokyo
  • A. Kiyomichi
    JAEA/J-PARC, Tokai-Mura, Naka-Gun, Ibaraki-Ken
  • K. Noda
    NIRS, Chiba-shi
  A prototype data processing board for a digital spill control system has been made. The system is considered to be used to control proton beams in 50-GeV synchrotron rings of J-PARC. The prototype circuit board consists of four ADCs, two FPGAs, a DSP, memories, and four DACs. The four inputs of the processing board are assumed to be an intensity signal of the proton beam in the accelerator rings, a digital gate signal that indicates the duration of beam extraction, a spill signal that shows the intensity of the extracted proton beam, and a reserved signal. The resolution and maximum sampling speed of the ADC are 16 bit and 2.5 Msps, respectively. One of the FPGAs is Vartex-2 1000-4C, and a real-time power spectrum analyzer will be implemented. It analyzes the spill signal every 1ms or shorter period. The analyzed result reflects optimum parameters used in spill control by servo. The DSP takes charge of these digital servo processing. The DACs with 16-bit resolution drive control signals for magnet currents. The system has another FPGA for communication between the processing board and network. MicroBlase CPU core is implemented, and uCLinux is installed to use EPICS.